summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
authorMartin Roth <martin.roth@se-eng.com>2014-06-12 12:31:59 -0600
committerMartin Roth <gaumless@gmail.com>2014-06-18 22:24:54 +0200
commitde38eeaaa6d27b25efc5c7c8ea2b09090f9241f0 (patch)
tree8a7a291a4a7b153b92186e74c467747dcd6f117f /src/soc/intel
parentc0602d4cab34ee228465c2779dda400b367082b6 (diff)
fsp_baytrail: Add the default FSP location
The default FSP location needs to be in the chipset, not the mainboard. This was removed from the Bayley Bay mainboard in patch 41ea7230f7 reviewed at http://review.coreboot.org/#/c/5982/ Change-Id: Ia26ed34e1401cbd2303166628e7a4e357d79c874 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5985 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/fsp_baytrail/fsp/Kconfig10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_baytrail/fsp/Kconfig b/src/soc/intel/fsp_baytrail/fsp/Kconfig
index 5df6374d0d..09493250d8 100644
--- a/src/soc/intel/fsp_baytrail/fsp/Kconfig
+++ b/src/soc/intel/fsp_baytrail/fsp/Kconfig
@@ -29,3 +29,13 @@ config FSP_FILE
help
The path and filename of the Intel FSP binary for this platform.
+config FSP_LOC
+ hex "Intel FSP Binary location in CBFS"
+ default 0xfffc0000
+ help
+ The location in CBFS that the FSP is located. This must match the
+ value that is set in the FSP binary. If the FSP needs to be moved,
+ rebase the FSP with the Intel's BCT (tool).
+
+ The Bay Trail FSP is built with a preferred base address of
+ 0xFFFC0000.