soc/intel/alderlake: Add GPIOs for Alder Lake SOC

Add definitions for the GPIO pins on Alder Lake LP,
as well as GPIO IRQ routing information and supporting ACPI ASL.

For now, add the following 5 GPIO communities and 13 GPIO groups:

Comm. 0: GPP_B, GPP_T, GPP_A
Comm. 1: GPP_S, GPP_H, GPP_D
Comm. 2: GPD
Comm. 4: GPP_C, GPP_F, GPP_E, GPP_HVMOS
Comm. 5: GPP_R, GPP_SPI0

Change-Id: I77b9dcc46aceaf530e2054c9cacd7b026ebbb96b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>

7 files changed, 986 insertions, 12 deletions

diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc
index a0b0e36e46..7ea9301a35 100644
--- a/src/soc/intel/alderlake/Makefile.inc
+++ b/src/soc/intel/alderlake/Makefile.inc
@@ -12,11 +12,18 @@ bootblock-y += bootblock/cpu.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += espi.c
+bootblock-y += gpio.c
 bootblock-y += p2sb.c
 
 romstage-y += espi.c
+romstage-y += gpio.c
 romstage-y += meminit.c
 romstage-y += reset.c
+
+ramstage-y += gpio.c
+
+smm-y += gpio.c
+
 CPPFLAGS_common += -I$(src)/soc/intel/alderlake
 CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include
 endif
diff --git a/src/soc/intel/alderlake/acpi/gpio.asl b/src/soc/intel/alderlake/acpi/gpio.asl
new file mode 100644
index 0000000000..e21f6d5481
--- /dev/null
+++ b/src/soc/intel/alderlake/acpi/gpio.asl
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <intelblocks/gpio.h>
+#include <soc/gpio_defs.h>
+#include <soc/intel/common/acpi/gpio.asl>
+#include <soc/intel/common/block/acpi/acpi/gpio_op.asl>
+#include <soc/irq.h>
+#include <soc/pcr_ids.h>
+
+Device (GPIO)
+{
+	Name (_HID, CROS_GPIO_NAME)
+	Name (_UID, 0)
+	Name (_DDN, "GPIO Controller")
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0, COM0)
+		Memory32Fixed (ReadWrite, 0, 0, COM1)
+		Memory32Fixed (ReadWrite, 0, 0, COM4)
+		Memory32Fixed (ReadWrite, 0, 0, COM5)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+			{ GPIO_IRQ14 }
+	})
+	Method (_CRS, 0, NotSerialized)
+	{
+		/* GPIO Community 0 */
+		CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
+		CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
+		BAS0 = ^^PCRB (PID_GPIOCOM0)
+		LEN0 = GPIO_BASE_SIZE
+
+		/* GPIO Community 1 */
+		CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
+		CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
+		BAS1 = ^^PCRB (PID_GPIOCOM1)
+		LEN1 = GPIO_BASE_SIZE
+
+		/* GPIO Community 4 */
+		CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
+		CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
+		BAS4 = ^^PCRB (PID_GPIOCOM4)
+		LEN4 = GPIO_BASE_SIZE
+
+		/* GPIO Community 5 */
+		CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
+		CreateDWordField (^RBUF, ^COM5._LEN, LEN5)
+		BAS5 = ^^PCRB (PID_GPIOCOM5)
+		LEN5 = GPIO_BASE_SIZE
+
+		Return (RBUF)
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0xF)
+	}
+}
+
+/*
+ * Get GPIO DW0 Address
+ * Arg0 - GPIO Number
+ */
+Method (GADD, 1, NotSerialized)
+{
+	/* GPIO Community 0 */
+	If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END)
+	{
+		Local0 = PID_GPIOCOM0
+		Local1 = Arg0 - GPIO_COM0_START
+	}
+	/* GPIO Community 1 */
+	If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END)
+	{
+		Local0 = PID_GPIOCOM1
+		Local1 = Arg0 - GPIO_COM1_START
+	}
+	/* GPIO Community 2 */
+	If (Arg0 >= GPIO_COM2_START && Arg0 <= GPIO_COM2_END)
+	{
+		Local0 = PID_GPIOCOM2
+		Local1 = Arg0 - GPIO_COM2_START
+	}
+	/* GPIO Community 4 */
+	If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END)
+	{
+		Local0 = PID_GPIOCOM4
+		Local1 = Arg0 - GPIO_COM4_START
+	}
+	/* GPIO Community 5*/
+	If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END)
+	{
+		Local0 = PID_GPIOCOM5
+		Local1 = Arg0 - GPIO_COM5_START
+	}
+
+	Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16)
+	Return (Local2)
+}
+
+/*
+ * Return PCR Port ID of GPIO Communities
+ *
+ * Arg0: GPIO Community (0-5)
+ */
+Method (GPID, 1, Serialized)
+{
+	Switch (ToInteger (Arg0))
+	{
+		Case (COMM_0) {
+			Local0 = PID_GPIOCOM0
+		}
+		Case (COMM_1) {
+			Local0 = PID_GPIOCOM1
+		}
+		Case (COMM_2) {
+			Local0 = PID_GPIOCOM2
+		}
+		Case (COMM_4) {
+			Local0 = PID_GPIOCOM4
+		}
+		Case (COMM_5) {
+			Local0 = PID_GPIOCOM5
+		}
+		Default {
+			Return (0)
+		}
+	}
+
+	Return (Local0)
+}
+
+/* GPIO Power Management bits */
+Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0})
+
+/*
+ * Save GPIO Power Management bits
+ */
+Method (SGPM, 0, Serialized)
+{
+	For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
+	{
+		Local1 = GPID (Local0)
+		GPMB[Local0] = PCRR (Local1, GPIO_MISCCFG)
+	}
+}
+
+/*
+ * Restore GPIO Power Management bits
+ */
+Method (RGPM, 0, Serialized)
+{
+	For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
+	{
+		CGPM (Local0, DerefOf(GPMB[Local0]))
+	}
+}
+
+/*
+ * Save current setting of GPIO Power Management bits and
+ * enable all Power Management bits for all communities
+ */
+Method (EGPM, 0, Serialized)
+{
+	/* Save current setting and will restore it when resuming */
+	SGPM ()
+	/* Enable PM bits */
+	For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
+	{
+		CGPM (Local0, MISCCFG_ENABLE_GPIO_PM_CONFIG)
+	}
+}
diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c
new file mode 100644
index 0000000000..f0db5e996b
--- /dev/null
+++ b/src/soc/intel/alderlake/gpio.c
@@ -0,0 +1,188 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <intelblocks/gpio.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+#include <soc/pmc.h>
+
+/*
+ * This file is created based on Intel Alder Lake Processor PCH Datasheet
+ * Document number: 630094
+ * Chapter number: 27
+ */
+
+static const struct reset_mapping rst_map[] = {
+	{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+};
+static const struct reset_mapping rst_map_com2[] = {
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
+};
+
+/*
+ * The GPIO pinctrl driver for Alder Lake on Linux expects 32 GPIOs per pad
+ * group, regardless of whether or not there is a physical pad for each
+ * exposed GPIO number.
+ *
+ * This results in the OS having a sparse GPIO map, and devices that need
+ * to export an ACPI GPIO must use the OS expected number.
+ *
+ * Not all pins are usable as GPIO and those groups do not have a pad base.
+ */
+static const struct pad_group adl_community0_groups[] = {
+	INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B25, 0),			/* GPP_B */
+	INTEL_GPP_BASE(GPP_B0, GPP_T0, GPP_T15, 32),			/* GPP_T */
+	INTEL_GPP_BASE(GPP_B0, GPP_A0, GPP_ESPI_CLK_LOOPBK, 64),	/* GPP_A */
+};
+
+static const struct pad_group adl_community1_groups[] = {
+	INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96),			/* GPP_S */
+	INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128),			/* GPP_H */
+	INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160),	/* GPP_D */
+};
+
+/* This community is not visible to the OS */
+static const struct pad_group adl_community2_groups[] = {
+	INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB),				/* GPD */
+};
+
+static const struct pad_group adl_community4_groups[] = {
+	INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256),			/* GPP_C */
+	INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 288),		/* GPP_F */
+	INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB),			/* GPP_HVMOS */
+	INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK, 320),		/* GPP_E */
+};
+
+static const struct pad_group adl_community5_groups[] = {
+	INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 352),			/* GPP_R */
+	INTEL_GPP(GPP_R0, GPP_SPI0_IO_2, GPP_SPI0_CLK),			/* GPP_SPI0 */
+};
+
+static const struct pad_community adl_communities[] = {
+	[COMM_0] = { /* GPP B, T, A */
+		.port = PID_GPIOCOM0,
+		.first_pad = GPIO_COM0_START,
+		.last_pad = GPIO_COM0_END,
+		.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
+		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_BTA",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = adl_community0_groups,
+		.num_groups = ARRAY_SIZE(adl_community0_groups),
+	},
+	[COMM_1] = { /* GPP S, D, H */
+		.port = PID_GPIOCOM1,
+		.first_pad = GPIO_COM1_START,
+		.last_pad = GPIO_COM1_END,
+		.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
+		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_SDH",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = adl_community1_groups,
+		.num_groups = ARRAY_SIZE(adl_community1_groups),
+	},
+	[COMM_2] = { /* GPD */
+		.port = PID_GPIOCOM2,
+		.first_pad = GPIO_COM2_START,
+		.last_pad = GPIO_COM2_END,
+		.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
+		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPD",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map_com2,
+		.num_reset_vals = ARRAY_SIZE(rst_map_com2),
+		.groups = adl_community2_groups,
+		.num_groups = ARRAY_SIZE(adl_community2_groups),
+	},
+	[COMM_4] = { /* GPP F, C, HVMOS, E */
+		.port = PID_GPIOCOM4,
+		.first_pad = GPIO_COM4_START,
+		.last_pad = GPIO_COM4_END,
+		.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
+		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_FCE",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = adl_community4_groups,
+		.num_groups = ARRAY_SIZE(adl_community4_groups),
+	},
+	[COMM_5] = { /* GPP R, SPI0 */
+		.port = PID_GPIOCOM5,
+		.first_pad = GPIO_COM5_START,
+		.last_pad = GPIO_COM5_END,
+		.num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
+		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPP_RSPI0",
+		.acpi_path = "\\_SB.PCI0.GPIO",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = adl_community5_groups,
+		.num_groups = ARRAY_SIZE(adl_community5_groups),
+	}
+};
+
+const struct pad_community *soc_gpio_get_community(size_t *num_communities)
+{
+	*num_communities = ARRAY_SIZE(adl_communities);
+	return adl_communities;
+}
+
+const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
+{
+	static const struct pmc_to_gpio_route routes[] = {
+		{ PMC_GPP_B,     GPP_B },
+		{ PMC_GPP_T,     GPP_T },
+		{ PMC_GPP_A,     GPP_A },
+		{ PMC_GPP_S,     GPP_S },
+		{ PMC_GPP_H,     GPP_H },
+		{ PMC_GPP_D,     GPP_D },
+		{ PMC_GPD,       GPD },
+		{ PMC_GPP_C,     GPP_C },
+		{ PMC_GPP_F,     GPP_F },
+		{ PMC_GPP_HVMOS, GPP_HVMOS },
+		{ PMC_GPP_E,     GPP_E },
+		{ PMC_GPP_R,     GPP_R },
+		{ PMC_GPP_SPI0,  GPP_SPI0 },
+	};
+	*num = ARRAY_SIZE(routes);
+	return routes;
+}
diff --git a/src/soc/intel/alderlake/include/soc/gpio.h b/src/soc/intel/alderlake/include/soc/gpio.h
new file mode 100644
index 0000000000..eec698a1e7
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/gpio.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ALDERLAKE_GPIO_H_
+#define _SOC_ALDERLAKE_GPIO_H_
+
+#include <soc/gpio_defs.h>
+#include <intelblocks/gpio.h>
+
+#define CROS_GPIO_NAME		"INTC1055"
+#define CROS_GPIO_DEVICE_NAME	"INTC1055:00"
+
+#endif
diff --git a/src/soc/intel/alderlake/include/soc/gpio_defs.h b/src/soc/intel/alderlake/include/soc/gpio_defs.h
new file mode 100644
index 0000000000..68b886acac
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/gpio_defs.h
@@ -0,0 +1,273 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ALDERLAKE_GPIO_DEFS_H_
+#define _SOC_ALDERLAKE_GPIO_DEFS_H_
+
+#ifndef __ACPI__
+#include <stddef.h>
+#endif
+#include <soc/gpio_soc_defs.h>
+
+#define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
+
+#define NUM_GPIO_COMx_GPI_REGS(n)	\
+		(ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
+#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
+#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
+#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
+#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS)
+
+#define NUM_GPI_STATUS_REGS	\
+		((NUM_GPIO_COM0_GPI_REGS) +\
+		(NUM_GPIO_COM1_GPI_REGS) +\
+		(NUM_GPIO_COM2_GPI_REGS) +\
+		(NUM_GPIO_COM4_GPI_REGS) +\
+		(NUM_GPIO_COM5_GPI_REGS))
+/*
+ * IOxAPIC IRQs for the GPIOs
+ */
+
+/* Group T */
+#define GPP_T0_IRQ				0x30
+#define GPP_T1_IRQ				0x31
+#define GPP_T2_IRQ				0x32
+#define GPP_T3_IRQ				0x33
+#define GPP_T4_IRQ				0x34
+#define GPP_T5_IRQ				0x35
+#define GPP_T6_IRQ				0x36
+#define GPP_T7_IRQ				0x37
+#define GPP_T8_IRQ				0x38
+#define GPP_T9_IRQ				0x39
+#define GPP_T10_IRQ				0x3A
+#define GPP_T11_IRQ				0x3B
+#define GPP_T12_IRQ				0x3C
+#define GPP_T13_IRQ				0x3D
+#define GPP_T14_IRQ				0x3E
+#define GPP_T15_IRQ				0x3F
+
+/* Group A */
+#define GPP_A0_IRQ				0x40
+#define GPP_A1_IRQ				0x41
+#define GPP_A2_IRQ				0x42
+#define GPP_A3_IRQ				0x43
+#define GPP_A4_IRQ				0x44
+#define GPP_A5_IRQ				0x45
+#define GPP_A6_IRQ				0x46
+#define GPP_A7_IRQ				0x47
+#define GPP_A8_IRQ				0x48
+#define GPP_A9_IRQ				0x49
+#define GPP_A10_IRQ				0x4A
+#define GPP_A11_IRQ				0x4B
+#define GPP_A12_IRQ				0x4C
+#define GPP_A13_IRQ				0x4D
+#define GPP_A14_IRQ				0x4E
+#define GPP_A15_IRQ				0x4F
+#define GPP_A16_IRQ				0x50
+#define GPP_A17_IRQ				0x51
+#define GPP_A18_IRQ				0x52
+#define GPP_A19_IRQ				0x53
+#define GPP_A20_IRQ				0x54
+#define GPP_A21_IRQ				0x55
+#define GPP_A22_IRQ				0x56
+#define GPP_A23_IRQ				0x57
+
+/* Group B */
+#define GPP_B0_IRQ				0x18
+#define GPP_B1_IRQ				0x19
+#define GPP_B2_IRQ				0x1A
+#define GPP_B3_IRQ				0x1B
+#define GPP_B4_IRQ				0x1C
+#define GPP_B5_IRQ				0x1D
+#define GPP_B6_IRQ				0x1E
+#define GPP_B7_IRQ				0x1F
+#define GPP_B8_IRQ				0x20
+#define GPP_B9_IRQ				0x21
+#define GPP_B10_IRQ				0x22
+#define GPP_B11_IRQ				0x23
+#define GPP_B12_IRQ				0x24
+#define GPP_B13_IRQ				0x25
+#define GPP_B14_IRQ				0x26
+#define GPP_B15_IRQ				0x27
+#define GPP_B16_IRQ				0x28
+#define GPP_B17_IRQ				0x29
+#define GPP_B18_IRQ				0x2A
+#define GPP_B19_IRQ				0x2B
+#define GPP_B20_IRQ				0x2C
+#define GPP_B21_IRQ				0x2D
+#define GPP_B22_IRQ				0x2E
+#define GPP_B23_IRQ				0x2F
+
+/* Group C */
+#define GPP_C0_iIRQ				0x6E
+#define GPP_C1_IRQ				0x6F
+#define GPP_C2_IRQ				0x70
+#define GPP_C3_IRQ				0x71
+#define GPP_C4_IRQ				0x72
+#define GPP_C5_IRQ				0x73
+#define GPP_C6_IRQ				0x74
+#define GPP_C7_IRQ				0x75
+#define GPP_C8_IRQ				0x76
+#define GPP_C9_IRQ				0x77
+#define GPP_C10_IRQ				0x18
+#define GPP_C11_IRQ				0x19
+#define GPP_C12_IRQ				0x1A
+#define GPP_C13_IRQ				0x1B
+#define GPP_C14_IRQ				0x1C
+#define GPP_C15_IRQ				0x1D
+#define GPP_C16_IRQ				0x1E
+#define GPP_C17_IRQ				0x1F
+#define GPP_C18_IRQ				0x20
+#define GPP_C19_IRQ				0x21
+#define GPP_C20_IRQ				0x22
+#define GPP_C21_IRQ				0x23
+#define GPP_C22_IRQ				0x24
+#define GPP_C23_IRQ				0x25
+
+/* Group D */
+#define GPP_D0_IRQ				0x2C
+#define GPP_D1_IRQ				0x2D
+#define GPP_D2_IRQ				0x2E
+#define GPP_D3_IRQ				0x2F
+#define GPP_D4_IRQ				0x30
+#define GPP_D5_IRQ				0x31
+#define GPP_D6_IRQ				0x32
+#define GPP_D7_IRQ				0x33
+#define GPP_D8_IRQ				0x34
+#define GPP_D9_IRQ				0x35
+#define GPP_D10_IRQ				0x36
+#define GPP_D11_IRQ				0x37
+#define GPP_D12_IRQ				0x38
+#define GPP_D13_IRQ				0x39
+#define GPP_D14_IRQ				0x3A
+#define GPP_D15_IRQ				0x3B
+#define GPP_D16_IRQ				0x3C
+#define GPP_D17_IRQ				0x3D
+#define GPP_D18_IRQ				0x3E
+#define GPP_D19_IRQ				0x3F
+
+/* Group E */
+#define GPP_E0_IRQ				0x26
+#define GPP_E1_IRQ				0x27
+#define GPP_E2_IRQ				0x28
+#define GPP_E3_IRQ				0x29
+#define GPP_E4_IRQ				0x30
+#define GPP_E5_IRQ				0x31
+#define GPP_E6_IRQ				0x32
+#define GPP_E7_IRQ				0x33
+#define GPP_E8_IRQ				0x34
+#define GPP_E9_IRQ				0x35
+#define GPP_E10_IRQ				0x36
+#define GPP_E11_IRQ				0x37
+#define GPP_E12_IRQ				0x38
+#define GPP_E13_IRQ				0x39
+#define GPP_E14_IRQ				0x3A
+#define GPP_E15_IRQ				0x3B
+#define GPP_E16_IRQ				0x3C
+#define GPP_E17_IRQ				0x3D
+#define GPP_E18_IRQ				0x3E
+#define GPP_E19_IRQ				0x3F
+#define GPP_E20_IRQ				0x40
+#define GPP_E21_IRQ				0x41
+#define GPP_E22_IRQ				0x42
+#define GPP_E23_IRQ				0x43
+
+/* Group F */
+#define GPP_F0_IRQ				0x56
+#define GPP_F1_IRQ				0x57
+#define GPP_F2_IRQ				0x58
+#define GPP_F3_IRQ				0x59
+#define GPP_F4_IRQ				0x5A
+#define GPP_F5_IRQ				0x5B
+#define GPP_F6_IRQ				0x5C
+#define GPP_F7_IRQ				0x5D
+#define GPP_F8_IRQ				0x5E
+#define GPP_F9_IRQ				0x5F
+#define GPP_F10_IRQ				0x60
+#define GPP_F11_IRQ				0x61
+#define GPP_F12_IRQ				0x62
+#define GPP_F13_IRQ				0x63
+#define GPP_F14_IRQ				0x64
+#define GPP_F15_IRQ				0x65
+#define GPP_F16_IRQ				0x66
+#define GPP_F17_IRQ				0x67
+#define GPP_F18_IRQ				0x68
+#define GPP_F19_IRQ				0x69
+#define GPP_F20_IRQ				0x6A
+#define GPP_F21_IRQ				0x6B
+#define GPP_F22_IRQ				0x6C
+#define GPP_F23_IRQ				0x6D
+
+/* Group H */
+#define GPP_H0_IRQ				0x74
+#define GPP_H1_IRQ				0x75
+#define GPP_H2_IRQ				0x76
+#define GPP_H3_IRQ				0x77
+#define GPP_H4_IRQ				0x18
+#define GPP_H5_IRQ				0x19
+#define GPP_H6_IRQ				0x1A
+#define GPP_H7_IRQ				0x1B
+#define GPP_H8_IRQ				0x1C
+#define GPP_H9_IRQ				0x1D
+#define GPP_H10_IRQ				0x1E
+#define GPP_H11_IRQ				0x1F
+#define GPP_H12_IRQ				0x20
+#define GPP_H13_IRQ				0x21
+#define GPP_H14_IRQ				0x22
+#define GPP_H15_IRQ				0x23
+#define GPP_H16_IRQ				0x24
+#define GPP_H17_IRQ				0x25
+#define GPP_H18_IRQ				0x26
+#define GPP_H19_IRQ				0x27
+#define GPP_H20_IRQ				0x28
+#define GPP_H21_IRQ				0x29
+#define GPP_H22_IRQ				0x2A
+#define GPP_H23_IRQ				0x2B
+
+/* Group R */
+#define GPP_R0_IRQ				0x58
+#define GPP_R1_IRQ				0x59
+#define GPP_R2_IRQ				0x5A
+#define GPP_R3_IRQ				0x5B
+#define GPP_R4_IRQ				0x5C
+#define GPP_R5_IRQ				0x5D
+#define GPP_R6_IRQ				0x5E
+#define GPP_R7_IRQ				0x5F
+
+/* Group S */
+#define GPP_S0_IRQ				0x6C
+#define GPP_S1_IRQ				0x6D
+#define GPP_S2_IRQ				0x6E
+#define GPP_S3_IRQ				0x6F
+#define GPP_S4_IRQ				0x70
+#define GPP_S5_IRQ				0x71
+#define GPP_S6_IRQ				0x72
+#define GPP_S7_IRQ				0x73
+
+/* Group GPD */
+#define GPD0_IRQ				0x60
+#define GPD1_IRQ				0x61
+#define GPD2_IRQ				0x62
+#define GPD3_IRQ				0x63
+#define GPD4_IRQ				0x64
+#define GPD5_IRQ				0x65
+#define GPD6_IRQ				0x66
+#define GPD7_IRQ				0x67
+#define GPD8_IRQ				0x68
+#define GPD9_IRQ				0x69
+#define GPD10_IRQ				0x6A
+#define GPD11_IRQ				0x6B
+
+/* Register defines. */
+#define GPIO_MISCCFG				0x10
+#define  GPE_DW_SHIFT				8
+#define  GPE_DW_MASK				0xfff00
+#define HOSTSW_OWN_REG_0			0xb0
+#define GPI_INT_STS_0				0x100
+#define GPI_INT_EN_0				0x110
+#define GPI_SMI_STS_0				0x180
+#define GPI_SMI_EN_0				0x1A0
+#define PAD_CFG_BASE				0x700
+
+#endif
diff --git a/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h
new file mode 100644
index 0000000000..bf95716a5d
--- /dev/null
+++ b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h
@@ -0,0 +1,322 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef _SOC_ALDERLAKE_GPIO_SOC_DEFS_H_
+#define _SOC_ALDERLAKE_GPIO_SOC_DEFS_H_
+
+/*
+ * Most of the fixed numbers and macros are based on the GPP groups.
+ * The GPIO groups are accessed through register blocks called
+ * communities.
+ */
+/* GPIO COMM 0 */
+#define GPP_B			0x0
+#define GPP_T			0x1
+#define GPP_A			0x2
+/* GPIO COMM 1 */
+#define GPP_S			0x3
+#define GPP_H			0x4
+#define GPP_D			0x5
+/* GPIO COMM 2 */
+#define GPD			0x6
+/* GPIO COMM 4 */
+#define GPP_C			0x7
+#define GPP_F			0x8
+#define GPP_HVMOS		0x9
+#define GPP_E			0xA
+/* GPIO COMM 5 */
+#define GPP_R			0xB
+#define GPP_SPI0		0xC
+
+#define GPIO_MAX_NUM_PER_GROUP	26
+
+#define COMM_0			0
+#define COMM_1			1
+#define COMM_2			2
+/* GPIO community 3 is not exposed to be used and hence is skipped. */
+#define COMM_4			3
+#define COMM_5			4
+/*
+ * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
+ */
+/* Group B */
+#define GPP_B0			0
+#define GPP_B1			1
+#define GPP_B2			2
+#define GPP_B3			3
+#define GPP_B4			4
+#define GPP_B5			5
+#define GPP_B6			6
+#define GPP_B7			7
+#define GPP_B8			8
+#define GPP_B9			9
+#define GPP_B10			10
+#define GPP_B11			11
+#define GPP_B12			12
+#define GPP_B13			13
+#define GPP_B14			14
+#define GPP_B15			15
+#define GPP_B16			16
+#define GPP_B17			17
+#define GPP_B18			18
+#define GPP_B19			19
+#define GPP_B20			20
+#define GPP_B21			21
+#define GPP_B22			22
+#define GPP_B23			23
+#define GPP_B24			24 /* GSPI0_CLK_LOOPBK */
+#define GPP_B25			25 /* GSPI1_CLK_LOOPBK */
+
+/* Group T */
+#define GPP_T0			26
+#define GPP_T1			27
+#define GPP_T2			28
+#define GPP_T3			29
+#define GPP_T4			30
+#define GPP_T5			31
+#define GPP_T6			32
+#define GPP_T7			33
+#define GPP_T8			34
+#define GPP_T9			35
+#define GPP_T10			36
+#define GPP_T11			37
+#define GPP_T12			38
+#define GPP_T13			39
+#define GPP_T14			40
+#define GPP_T15			41
+
+/* Group A */
+#define GPP_A0			42
+#define GPP_A1			43
+#define GPP_A2			44
+#define GPP_A3			45
+#define GPP_A4			46
+#define GPP_A5			47
+#define GPP_A6			48
+#define GPP_A7			49
+#define GPP_A8			50
+#define GPP_A9			51
+#define GPP_A10			52
+#define GPP_A11			53
+#define GPP_A12			54
+#define GPP_A13			55
+#define GPP_A14			56
+#define GPP_A15			57
+#define GPP_A16			58
+#define GPP_A17			59
+#define GPP_A18			60
+#define GPP_A19			61
+#define GPP_A20			62
+#define GPP_A21			63
+#define GPP_A22			64
+#define GPP_A23			65
+#define GPP_ESPI_CLK_LOOPBK	66
+
+#define GPIO_COM0_START		GPP_B0
+#define GPIO_COM0_END		GPP_ESPI_CLK_LOOPBK
+#define NUM_GPIO_COM0_PADS	(GPIO_COM0_END - GPIO_COM0_START + 1)
+
+/* Group S */
+#define GPP_S0			67
+#define GPP_S1			68
+#define GPP_S2			69
+#define GPP_S3			70
+#define GPP_S4			71
+#define GPP_S5			72
+#define GPP_S6			73
+#define GPP_S7			74
+
+/* Group H */
+#define GPP_H0			75
+#define GPP_H1			76
+#define GPP_H2			77
+#define GPP_H3			78
+#define GPP_H4			79
+#define GPP_H5			80
+#define GPP_H6			81
+#define GPP_H7			82
+#define GPP_H8			83
+#define GPP_H9			84
+#define GPP_H10			85
+#define GPP_H11			86
+#define GPP_H12			87
+#define GPP_H13			88
+#define GPP_H14			89
+#define GPP_H15			90
+#define GPP_H16			91
+#define GPP_H17			92
+#define GPP_H18			93
+#define GPP_H19			94
+#define GPP_H20			95
+#define GPP_H21			96
+#define GPP_H22			97
+#define GPP_H23			98
+
+/* Group D */
+#define GPP_D0			99
+#define GPP_D1			100
+#define GPP_D2			101
+#define GPP_D3			102
+#define GPP_D4			103
+#define GPP_D5			104
+#define GPP_D6			105
+#define GPP_D7			106
+#define GPP_D8			107
+#define GPP_D9			108
+#define GPP_D10			109
+#define GPP_D11			110
+#define GPP_D12			111
+#define GPP_D13			112
+#define GPP_D14			113
+#define GPP_D15			114
+#define GPP_D16			115
+#define GPP_D17			116
+#define GPP_D18			117
+#define GPP_D19			118
+#define GPP_GSPI2_CLK_LOOPBK	119
+
+#define GPIO_COM1_START		GPP_S0
+#define GPIO_COM1_END		GPP_GSPI2_CLK_LOOPBK
+#define NUM_GPIO_COM1_PADS	(GPIO_COM1_END - GPIO_COM1_START + 1)
+
+/* Group GPD */
+#define GPD0			120
+#define GPD1			121
+#define GPD2			122
+#define GPD3			123
+#define GPD4			124
+#define GPD5			125
+#define GPD6			126
+#define GPD7			127
+#define GPD8			128
+#define GPD9			129
+#define GPD10			130
+#define GPD11			131
+#define GPD_INPUT3VSEL		132
+#define GPD_SLP_LANB		133
+#define GPD_SLP_SUSB		134
+#define GPD_WAKEB		135
+#define GPD_DRAM_RESETB		136
+
+#define GPIO_COM2_START		GPD0
+#define GPIO_COM2_END		GPD_DRAM_RESETB
+#define NUM_GPIO_COM2_PADS	(GPIO_COM2_END - GPIO_COM2_START + 1)
+
+/* Group C */
+#define GPP_C0			137
+#define GPP_C1			138
+#define GPP_C2			139
+#define GPP_C3			140
+#define GPP_C4			141
+#define GPP_C5			142
+#define GPP_C6			143
+#define GPP_C7			144
+#define GPP_C8			145
+#define GPP_C9			146
+#define GPP_C10			147
+#define GPP_C11			148
+#define GPP_C12			149
+#define GPP_C13			150
+#define GPP_C14			151
+#define GPP_C15			152
+#define GPP_C16			153
+#define GPP_C17			154
+#define GPP_C18			155
+#define GPP_C19			156
+#define GPP_C20			157
+#define GPP_C21			158
+#define GPP_C22			159
+#define GPP_C23			160
+
+/* Group F */
+#define GPP_F0			161
+#define GPP_F1			162
+#define GPP_F2			163
+#define GPP_F3			164
+#define GPP_F4			165
+#define GPP_F5			166
+#define GPP_F6			167
+#define GPP_F7			168
+#define GPP_F8			169
+#define GPP_F9			170
+#define GPP_F10			171
+#define GPP_F11			172
+#define GPP_F12			173
+#define GPP_F13			174
+#define GPP_F14			175
+#define GPP_F15			176
+#define GPP_F16			177
+#define GPP_F17			178
+#define GPP_F18			179
+#define GPP_F19			180
+#define GPP_F20			181
+#define GPP_F21			182
+#define GPP_F22			183
+#define GPP_F23			184
+#define GPP_F_CLK_LOOPBK	185
+
+/* Group HVMOS */
+#define GPP_L_BKLTEN		186
+#define GPP_L_BKLTCTL		187
+#define GPP_L_VDDEN		188
+#define GPP_SYS_PWROK		189
+#define GPP_SYS_RESETB		190
+#define GPP_MLK_RSTB		191
+
+/* Group E */
+#define GPP_E0			192
+#define GPP_E1			193
+#define GPP_E2			194
+#define GPP_E3			195
+#define GPP_E4			196
+#define GPP_E5			197
+#define GPP_E6			198
+#define GPP_E7			199
+#define GPP_E8			200
+#define GPP_E9			201
+#define GPP_E10			202
+#define GPP_E11			203
+#define GPP_E12			204
+#define GPP_E13			205
+#define GPP_E14			206
+#define GPP_E15			207
+#define GPP_E16			208
+#define GPP_E17			209
+#define GPP_E18			210
+#define GPP_E19			211
+#define GPP_E20			212
+#define GPP_E21			213
+#define GPP_E22			214
+#define GPP_E23			215
+#define GPP_E_CLK_LOOPBK	216
+
+#define GPIO_COM4_START		GPP_C0
+#define GPIO_COM4_END		GPP_E_CLK_LOOPBK
+#define NUM_GPIO_COM4_PADS	(GPIO_COM4_END - GPIO_COM4_START + 1)
+
+/* Group R */
+#define GPP_R0			217
+#define GPP_R1			218
+#define GPP_R2			219
+#define GPP_R3			220
+#define GPP_R4			221
+#define GPP_R5			222
+#define GPP_R6			223
+#define GPP_R7			224
+
+/* Group SPI0 */
+#define GPP_SPI0_IO_2		225
+#define GPP_SPI0_IO_3		226
+#define GPP_SPI0_MOSI_IO_0	227
+#define GPP_SPI0_MOSI_IO_1	228
+#define GPP_SPI0_TPM_CSB	229
+#define GPP_SPI0_FLASH_0_CSB	230
+#define GPP_SPI0_FLASH_1_CSB	231
+#define GPP_SPI0_CLK		232
+
+#define GPIO_COM5_START		GPP_R0
+#define GPIO_COM5_END		GPP_SPI0_CLK
+#define NUM_GPIO_COM5_PADS	(GPIO_COM5_END - GPIO_COM5_START + 1)
+
+#define TOTAL_GPIO_COMM		(COMM_5 + 1)
+#define TOTAL_PADS		(GPIO_COM5_END + 1)
+
+#endif
diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h
index f1100708c8..03fe02fee1 100644
--- a/src/soc/intel/alderlake/include/soc/pmc.h
+++ b/src/soc/intel/alderlake/include/soc/pmc.h
@@ -126,18 +126,19 @@ enum pch_pmc_xtal pmc_get_xtal_freq(void);
 #define  GPE0_DWX_MASK			0xf
 #define  GPE0_DW_SHIFT(x)		(4*(x))
 
-#define  PMC_GPP_B		0x0
-#define  PMC_GPP_T		0x1
-#define  PMC_GPP_A		0x2
-#define  PMC_GPP_R		0x3
-#define  PMC_GPD		0x4
-#define  PMC_GPP_S		0x5
-#define  PMC_GPP_H		0x6
-#define  PMC_GPP_D		0x7
-#define  PMC_GPP_U		0x8
-#define  PMC_GPP_F		0xA
-#define  PMC_GPP_C		0xB
-#define  PMC_GPP_E		0xC
+#define PMC_GPP_B		0x0
+#define PMC_GPP_T		0x1
+#define PMC_GPP_A		0x2
+#define PMC_GPP_S		0x3
+#define PMC_GPP_H		0x4
+#define PMC_GPP_D		0x5
+#define PMC_GPD			0x6
+#define PMC_GPP_C		0x7
+#define PMC_GPP_F		0x8
+#define PMC_GPP_HVMOS		0x9
+#define PMC_GPP_E		0xA
+#define PMC_GPP_R		0xB
+#define PMC_GPP_SPI0		0xC
 
 #define GBLRST_CAUSE0			0x1924
 #define   GBLRST_CAUSE0_THERMTRIP	(1 << 5)