diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-11-10 09:57:19 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-12-10 17:47:03 +0000 |
| commit | a7b60e7dc8788db5de2fe983e9702e167b7f27fe (patch) | |
| tree | 344a8b066b6df40518a6bc15ba3ef5a75df1d924 /src/soc/intel | |
| parent | 56fcfb5b4f00830d0c1bf2230e1104045d795c82 (diff) | |
soc/intel/tigerlake: Check TBT & TCSS ports for wake events
Wakes from TBT ports and TCSS devices will show up as PME_B0_STS wakes,
so add checks for wakes from these devices in
pch_log_pme_internal_wake_source.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie9904c3c01ea85fcd83218fcfeaa4378b07c1463
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47396
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/tigerlake/elog.c | 37 |
1 files changed, 31 insertions, 6 deletions
diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 531f5c11ee..7f40a37d2f 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -60,12 +60,13 @@ static void pch_log_rp_wake_source(void) static void pch_log_pme_internal_wake_source(void) { const struct pme_map ipme_map[] = { - { PCH_DEVFN_HDA, ELOG_WAKE_SOURCE_PME_HDA }, - { PCH_DEVFN_GBE, ELOG_WAKE_SOURCE_PME_GBE }, - { PCH_DEVFN_SATA, ELOG_WAKE_SOURCE_PME_SATA }, - { PCH_DEVFN_CSE, ELOG_WAKE_SOURCE_PME_CSE }, - { PCH_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI }, - { PCH_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI }, + { PCH_DEVFN_HDA, ELOG_WAKE_SOURCE_PME_HDA }, + { PCH_DEVFN_GBE, ELOG_WAKE_SOURCE_PME_GBE }, + { PCH_DEVFN_SATA, ELOG_WAKE_SOURCE_PME_SATA }, + { PCH_DEVFN_CSE, ELOG_WAKE_SOURCE_PME_CSE }, + { PCH_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI }, + { PCH_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI }, + { SA_DEVFN_TCSS_XDCI, ELOG_WAKE_SOURCE_PME_TCSS_XDCI }, }; const struct xhci_wake_info xhci_wake_info[] = { { PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, @@ -86,6 +87,30 @@ static void pch_log_pme_internal_wake_source(void) } } + /* Check Thunderbolt ports */ + for (i = 0; i < NUM_TBT_FUNCTIONS; i++) { + const struct device *dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TBT, i); + dev_found = true; + } + } + + /* Check DMA devices */ + for (i = 0; i < NUM_TCSS_DMA_FUNCTIONS; i++) { + const struct device *dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA(i)); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TCSS_DMA, i); + dev_found = true; + } + } + /* * Check the XHCI controllers' USB2 & USB3 ports for wake events. There * are cases (GSMI logging for S0ix clears PME_STS_BIT) where the XHCI |