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authorWilliam Wei <wenxu.wei@bitland.corp-partner.google.com>2020-06-22 13:30:37 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-06-29 15:49:04 +0000
commit9f6622fb5588a9322b7f1c71bc198d0c2e1dd1bf (patch)
treef1df01f559863fe8736d66fe975a0380d90c0a9e /src/soc/intel
parent3f2f5edfeddb340524166355df563a0632f70013 (diff)
soc/intel/tigerlake: Run pmc_set_acpi_mode() during .init in pmc_ops
pmc_set_acpi_mode() should run after Chrome EC dealt with all host event bits, like SMI mask (otherwise the FAFT firmware_FWScreenCloseLid test will fail). BUG=b:153249055 TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage Change the GBB flag to 0x140 then check SMI mask during depthcharge phase, make sure it's 0x0000000000000001. Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com> Change-Id: Icfff5cc5550f23938343e4d26ef76093bb9cf7c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/tigerlake/pmc.c17
1 files changed, 15 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c
index 4d898700bd..b98cbbe797 100644
--- a/src/soc/intel/tigerlake/pmc.c
+++ b/src/soc/intel/tigerlake/pmc.c
@@ -77,8 +77,6 @@ static void pmc_init(struct device *dev)
pmc_set_power_failure_state(true);
pmc_gpe_init();
- pmc_set_acpi_mode();
-
config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
config_deep_sx(config->deep_sx_config);
@@ -142,9 +140,24 @@ const struct device *soc_get_pmc_mux_device(int port_number)
return child;
}
+static void soc_acpi_mode_init(struct device *dev)
+{
+ /*
+ * pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order
+ * to ensure the ordering does not break the assumptions that other
+ * drivers make about ACPI mode (e.g. Chrome EC). Since it disables
+ * ACPI mode, other drivers may take different actions based on this
+ * (e.g. Chrome EC will flush any pending hostevent bits). Because
+ * TGL has its PMC device available for device_operations, it can be
+ * done from the "ops->init" callback.
+ */
+ pmc_set_acpi_mode();
+}
+
struct device_operations pmc_ops = {
.read_resources = soc_pmc_read_resources,
.set_resources = noop_set_resources,
+ .init = soc_acpi_mode_init,
.enable = pmc_init,
#if CONFIG(HAVE_ACPI_TABLES)
.acpi_fill_ssdt = soc_pmc_fill_ssdt,