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authorAngel Pons <th3fanbus@gmail.com>2020-08-03 12:29:41 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-08-04 21:43:45 +0000
commit96a80133e17c238d9f1566ea2cdc545445920968 (patch)
treee67bb10e3d8f492370ceace5acebbfa504284c50 /src/soc/intel
parent37799b34395254d02a68d00d6ab4a77ce6bc5341 (diff)
soc/intel/skylake: Add RMRRs after all DRHDs
The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says: BIOS implementations must report these remapping structure types in numerical order. i.e., All remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. So, update the corresponding code to adhere to the specification. Change-Id: I2446d536603559f637f3f8b1b44e9d712aa35492 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/skylake/acpi.c29
1 files changed, 18 insertions, 11 deletions
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 1beff3d3af..ae9d78436c 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -425,22 +425,19 @@ static unsigned long acpi_fill_dmar(unsigned long current)
const bool gfxvten = MCHBAR32(GFXVTBAR) & 1;
/* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */
- if (igfx_dev && igfx_dev->enabled && gfxvten &&
- gfx_vtbar && !MCHBAR32(GFXVTBAR + 4)) {
- unsigned long tmp = current;
+ const bool emit_igd =
+ igfx_dev && igfx_dev->enabled &&
+ gfx_vtbar && gfxvten &&
+ !MCHBAR32(GFXVTBAR + 4);
+
+ /* First, add DRHD entries */
+ if (emit_igd) {
+ const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar);
current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
acpi_dmar_drhd_fixup(tmp, current);
-
- /* Add RMRR entry */
- tmp = current;
-
- current += acpi_create_dmar_rmrr(current, 0,
- sa_get_gsm_base(), sa_get_tolud_base() - 1);
- current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
- acpi_dmar_rmrr_fixup(tmp, current);
}
const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
@@ -461,6 +458,16 @@ static unsigned long acpi_fill_dmar(unsigned long current)
acpi_dmar_drhd_fixup(tmp, current);
}
+ /* Then, add RMRR entries after all DRHD entries */
+ if (emit_igd) {
+ const unsigned long tmp = current;
+
+ current += acpi_create_dmar_rmrr(current, 0,
+ sa_get_gsm_base(), sa_get_tolud_base() - 1);
+ current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
+ acpi_dmar_rmrr_fixup(tmp, current);
+ }
+
return current;
}