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authorLijian Zhao <lijian.zhao@intel.com>2017-05-02 18:54:44 -0700
committerMartin Roth <martinroth@google.com>2017-06-29 14:50:38 +0000
commit81096041b8da42b17e57c63bdf81902b6ec69d61 (patch)
tree74c22da9b50c3a9cdb91ff8ed28aeae2bb07973c /src/soc/intel
parent786bd5d29371745bb731e92be0e73e261baf125e (diff)
soc/intel/cannonlake: Add initial dummy directory
Add Cannon Lake SoC boilerplate directory with: * SoC directory * Base Kconfig * Dummy cbmem.c Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/20061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/cannonlake/Kconfig67
-rw-r--r--src/soc/intel/cannonlake/Makefile.inc7
-rw-r--r--src/soc/intel/cannonlake/cbmem.c22
3 files changed, 96 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
new file mode 100644
index 0000000000..5da39b961f
--- /dev/null
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -0,0 +1,67 @@
+config SOC_INTEL_CANNONLAKE
+ bool
+ help
+ Intel Cannonlake support
+
+if SOC_INTEL_CANNONLAKE
+
+config CPU_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_BOOTBLOCK_X86_32
+ select ARCH_VERSTAGE_X86_32
+ select ARCH_RAMSTAGE_X86_32
+ select ARCH_ROMSTAGE_X86_32
+ select HAVE_MONOTONIC_TIMER
+ select TSC_CONSTANT_RATE
+ select TSC_MONOTONIC_TIMER
+ select UDELAY_TSC
+ select REG_SCRIPT
+ select C_ENVIRONMENT_BOOTBLOCK
+ select HAVE_HARD_RESET
+ select HAVE_INTEL_FIRMWARE
+ select INTEL_CAR_NEM_ENHANCED
+ select PLATFORM_USES_FSP2_0
+ select SOC_INTEL_COMMON
+ select SOC_INTEL_COMMON_BLOCK_SA
+ select SOC_INTEL_COMMON_BLOCK
+ select SOC_INTEL_COMMON_BLOCK_CAR
+ select SOC_INTEL_COMMON_RESET
+ select SOC_INTEL_COMMON_BLOCK_LPSS
+ select SOC_INTEL_COMMON_BLOCK_UART
+ select SOC_INTEL_COMMON_BLOCK_FAST_SPI
+ select SOC_INTEL_COMMON_BLOCK_PCR
+ select SOC_INTEL_COMMON_BLOCK_SMBUS
+ select SOC_INTEL_COMMON_BLOCK_RTC
+ select SOC_INTEL_COMMON_BLOCK_CSE
+
+config UART_DEBUG
+ bool "Enable UART debug port."
+ default y
+ select CONSOLE_SERIAL
+ select BOOTBLOCK_CONSOLE
+ select DRIVERS_UART
+ select DRIVERS_UART_8250IO
+
+config DCACHE_RAM_BASE
+ default 0xfef00000
+
+config DCACHE_RAM_SIZE
+ default 0x40000
+ help
+ The size of the cache-as-ram region required during bootblock
+ and/or romstage.
+
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x4000
+ help
+ The amount of anticipated stack usage in CAR by bootblock and
+ other stages.
+
+config PCR_BASE_ADDRESS
+ hex
+ default 0xfd000000
+ help
+ This option allows you to select MMIO Base Address of sideband bus.
+
+endif
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
new file mode 100644
index 0000000000..4651a23862
--- /dev/null
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -0,0 +1,7 @@
+ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y)
+
+romstage-y += cbmem.c
+
+ramstage-y += cbmem.c
+
+endif
diff --git a/src/soc/intel/cannonlake/cbmem.c b/src/soc/intel/cannonlake/cbmem.c
new file mode 100644
index 0000000000..0f47173061
--- /dev/null
+++ b/src/soc/intel/cannonlake/cbmem.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+
+void *cbmem_top(void)
+{
+ /* not implemented yet */
+ return (void *) NULL;
+}