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authorJohn Su <john_su@compal.corp-partner.google.com>2018-05-10 09:54:08 +0800
committerMartin Roth <martinroth@google.com>2018-05-15 15:50:20 +0000
commit77a30af41cd252bb72883f30e57683b1d11a8c36 (patch)
tree78c63fb501e45c1ff84796f50eaa6b6d1935ee1a /src/soc/intel
parent532b8d5f251758e88dfe5769fb8d925da7844f19 (diff)
soc/intel/skylake: check DPTF_TSR1_ACTIVE_AC* in _ACx methods
Because thermal table is not included the values of DPTF_TSR1_ACTIVE_AC from internal nami/vayne thermal team. Add conditional compilation in _ACx methods if DPTF_ENABLE_FAN_CONTROL is defined in the dptf.asl. BUG=b:72974136 TEST=Match the result. Change-Id: I4b593118ca460a59aa49786cb99df417d135112a Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/skylake/acpi/dptf/thermal.asl33
1 files changed, 33 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl
index 829039242c..f99b7c3fc7 100644
--- a/src/soc/intel/skylake/acpi/dptf/thermal.asl
+++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl
@@ -263,6 +263,39 @@ Device (TSR1)
{
\_SB.PCI0.LPCB.EC0.PATD (TMPI)
}
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+#ifdef DPTF_TSR1_ACTIVE_AC0
+ Method (_AC0)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0))
+ }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC1
+ Method (_AC1)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1))
+ }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC2
+ Method (_AC2)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2))
+ }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC3
+ Method (_AC3)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3))
+ }
+#endif
+#ifdef DPTF_TSR1_ACTIVE_AC4
+ Method (_AC4)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4))
+ }
+#endif
+#endif
}
#endif