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authorArthur Heymans <arthur@aheymans.xyz>2019-04-24 12:29:44 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-04-25 15:56:28 +0000
commit74f9fe6e58f949001a34866505cecca16aa0de03 (patch)
treea46a7d5f92669425a05f8394918c1b6be1e74c91 /src/soc/intel
parent5417c84f7d525d1db8f4abbf3ef4da527dd52cd6 (diff)
cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE
CPU's featuring a non eviction mode cache the whole ROM. Therefore XIP stages don't need to follow some alignment constraints. Change-Id: I4a30f31baa0f90279c0690ceb6aefea6de461bd9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/broadwell/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 5f503da340..25984f14e2 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -43,6 +43,7 @@ config CPU_SPECIFIC_OPTIONS
select POSTCAR_CONSOLE
select HAVE_POWER_STATE_AFTER_FAILURE
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
+ select NO_FIXED_XIP_ROM_SIZE
config PCIEXP_ASPM
bool