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authorFurquan Shaikh <furquan@chromium.org>2016-10-24 15:27:21 -0700
committerFurquan Shaikh <furquan@google.com>2016-10-26 01:50:45 +0200
commit723a84e2920c8ba52257cf4bf445b23ff01d8754 (patch)
tree86ea0f936ee6e9e16e878976a4ad511e7971ce99 /src/soc/intel
parentaedbfc8f0917b332e648fe6c4333567bd8e58b0d (diff)
soc/intel/skylake: Use intel common support to write-protect SPI flash
BUG=chrome-os-partner:58896 Change-Id: I281c799a1798f3353d78edd8a6cd16bbe762bc2c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17116 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/skylake/Kconfig1
-rw-r--r--src/soc/intel/skylake/flash_controller.c31
-rw-r--r--src/soc/intel/skylake/include/soc/spi.h12
3 files changed, 6 insertions, 38 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 5a1d878f90..a5fb0e8d84 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -44,6 +44,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_LPSS_I2C
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
+ select SOC_INTEL_COMMON_SPI_PROTECT
select SMM_TSEG
select SMP
select SSE2
diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c
index 6601e6caa3..56c7c69527 100644
--- a/src/soc/intel/skylake/flash_controller.c
+++ b/src/soc/intel/skylake/flash_controller.c
@@ -21,6 +21,7 @@
#include <spi_flash.h>
#include <timer.h>
#include <soc/flash_controller.h>
+#include <soc/intel/common/spi.h>
#include <soc/pci_devs.h>
#include <soc/spi.h>
@@ -386,40 +387,16 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
return slave;
}
-int spi_flash_protect(u32 start, u32 size)
+int spi_get_fpr_info(struct fpr_info *info)
{
pch_spi_regs *spi_bar = get_spi_bar();
- u32 end = start + size - 1;
- u32 reg;
- int prr;
if (!spi_bar)
return -1;
- /* Find first empty PRR */
- for (prr = 0; prr < SPI_PRR_MAX; prr++) {
- reg = read32(&spi_bar->pr[prr]);
- if (reg == 0)
- break;
- }
- if (prr >= SPI_PRR_MAX) {
- printk(BIOS_ERR, "ERROR: No SPI PRR free!\n");
- return -1;
- }
-
- /* Set protected range base and limit */
- reg = SPI_PRR(start, end) | SPI_PRR_WPE;
-
- /* Set the PRR register and verify it is protected */
- write32(&spi_bar->pr[prr], reg);
- reg = read32(&spi_bar->pr[prr]);
- if (!(reg & SPI_PRR_WPE)) {
- printk(BIOS_ERR, "ERROR: Unable to set SPI PRR %d\n", prr);
- return -1;
- }
+ info->base = (uintptr_t)&spi_bar->pr[0];
+ info->max = SPI_FPR_MAX;
- printk(BIOS_INFO, "%s: PRR %d is enabled for range 0x%08x-0x%08x\n",
- __func__, prr, start, end);
return 0;
}
diff --git a/src/soc/intel/skylake/include/soc/spi.h b/src/soc/intel/skylake/include/soc/spi.h
index c930b5818c..a92b78d0c9 100644
--- a/src/soc/intel/skylake/include/soc/spi.h
+++ b/src/soc/intel/skylake/include/soc/spi.h
@@ -40,16 +40,7 @@
/* STRAP Data Register*/
#define SPIBAR_RESET_DATA 0xF8
-#define SPI_PRR_MAX 5
-#define SPI_PRR_SHIFT 12
-#define SPI_PRR_MASK 0x7fff
-#define SPI_PRR_BASE_SHIFT 0
-#define SPI_PRR_LIMIT_SHIFT 16
-#define SPI_PRR_RPE (1 << 15) /* Read Protect */
-#define SPI_PRR_WPE (1 << 31) /* Write Protect */
-#define SPI_PRR(base, limit) \
- (((((limit) >> SPI_PRR_SHIFT) & SPI_PRR_MASK) << SPI_PRR_LIMIT_SHIFT) |\
- ((((base) >> SPI_PRR_SHIFT) & SPI_PRR_MASK) << SPI_PRR_BASE_SHIFT))
+#define SPI_FPR_MAX 5
#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
#define SPI_OPTYPE_0 0x01 /* Write, no address */
@@ -131,6 +122,5 @@
#define SPIBAR_BC_WPD (1 << 0)
void *get_spi_bar(void);
-int spi_flash_protect(u32 start, u32 size);
#endif