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authorArthur Heymans <arthur@aheymans.xyz>2019-05-23 15:07:49 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-05-29 20:18:43 +0000
commit56e2d7d21aeffb75af34606bc034ee4fed560775 (patch)
treed6c6ee8c465effb41697da412acaac4929adca60 /src/soc/intel
parent73ac12196c61c8d0c21a54dfa87b858662d6859a (diff)
soc/intel/skylake: Use common cpu/intel/car romstage code
Setting up the console and entering postcar can be done in a common place. Change-Id: I8a8db0fcb4f0fbbb121a8195a8a8b6644c28db07 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32962 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/skylake/romstage/Makefile.inc2
-rw-r--r--src/soc/intel/skylake/romstage/car_stage.S41
2 files changed, 1 insertions, 42 deletions
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 8bfbfea66a..e929ebaf17 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,4 +1,4 @@
-romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += car_stage.S
+romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += ../../../../cpu/intel/car/romstage.c
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c
romstage-y += systemagent.c
diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S
deleted file mode 100644
index d8b45cb258..0000000000
--- a/src/soc/intel/skylake/romstage/car_stage.S
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/x86/post_code.h>
-
-/* I/O delay between post codes on failure */
-#define LHLT_DELAY 0x50000
-
-.text
-.global car_stage_entry
-car_stage_entry:
- call romstage_c_entry
-
- /* we don't return here */
- movb $0x69, %ah
- jmp .Lhlt
-
-.Lhlt:
- xchg %al, %ah
-#if CONFIG(POST_IO)
- outb %al, $CONFIG_POST_IO_PORT
-#else
- post_code(POST_DEAD_CODE)
-#endif
- movl $LHLT_DELAY, %ecx
-.Lhlt_Delay:
- outb %al, $0xED
- loop .Lhlt_Delay
- jmp .Lhlt