diff options
| author | Martin Roth <gaumless@gmail.com> | 2015-04-16 21:20:34 -0600 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2015-04-28 20:50:03 +0200 |
| commit | 562d6f30a0745b3da4c61974f8ac1b529dac9d80 (patch) | |
| tree | fed954e864a211d8ecfcdfcadf105f7d2a4a3fac /src/soc/intel | |
| parent | ceae968e2cc3d9318c70e34a5424080f9f345eea (diff) | |
fsp platforms: consolidate FspNotify calls
Consolidate the FspNotify calls into the FSP driver directory,
using BOOT_STATE_INIT_ENTRY to set up the call times.
Change-Id: I184ab234ebb9dcdeb8eece1537c12d03f227c25e
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/9780
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/chip.c | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c index d26b64aa96..991e851d77 100644 --- a/src/soc/intel/fsp_baytrail/chip.c +++ b/src/soc/intel/fsp_baytrail/chip.c @@ -30,22 +30,11 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void finalize_dev (device_t dev) -{ - /* - * Notify FSP for PostPciEnumeration. - * Northbridge APIC init should be early and late enough... - */ - printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); - FspNotify(EnumInitPhaseAfterPciEnumeration); -} - static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, .enable_resources = NULL, .init = NULL, - .final = &finalize_dev, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, }; @@ -77,14 +66,6 @@ static void enable_dev(device_t dev) } } -static void finalize_chip(void *chip_info) -{ - /* Notify FSP for ReadyToBoot */ - printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n"); - FspNotify(EnumInitPhaseReadyToBoot); - -} - /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ static void soc_init(void *chip_info) { @@ -95,7 +76,6 @@ struct chip_operations soc_intel_fsp_baytrail_ops = { CHIP_NAME("Intel BayTrail SoC") .enable_dev = enable_dev, .init = soc_init, - .final = &finalize_chip, }; static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) |