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authorpraveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>2018-09-21 04:24:16 +0800
committerSubrata Banik <subrata.banik@intel.com>2018-09-21 02:21:40 +0000
commit338c8002d2a2d4335b9ebf0e5bcc5b3ca1ce35a4 (patch)
treef3cff2a002252f84f8c6aa32ba1c1535621cd700 /src/soc/intel
parentc423d7d8f1ecb0de79590f7cd7cb99a6dc0e73d8 (diff)
soc/intel/cannonlake: Correct ITSS port id.
According to cannon lake PCH BIOS specification document #570374 target port id for interrupt and timer subsystem(ITSS) is C4 instead of C2. BUG=None TEST=None Change-Id: I9f8783c682d2c4c4a86e1c9cf4b9c27a18fdf494 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Kin Wai Ng <nelsonaquik@gmail.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/cannonlake/include/soc/pcr_ids.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h
index 891b18742b..c4a18e8f90 100644
--- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h
@@ -35,7 +35,7 @@
#define PID_PSF4 0xbd
#define PID_SCS 0xc0
#define PID_RTC 0xc3
-#define PID_ITSS 0xc2
+#define PID_ITSS 0xc4
#define PID_LPC 0xc7
#define PID_SERIALIO 0xcb