diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-10-23 19:36:25 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-10-25 06:18:03 +0000 |
| commit | 28371e282690dd32ea78a52479331463215e18df (patch) | |
| tree | 67428e7f7f254ea640a372124d11c9a90d5a70dd /src/soc/intel | |
| parent | a8ddc89d27ed72cf328ef82f5f3c0bdbe6b9f7f1 (diff) | |
soc/intel/alderlake/romstage: Skip GPIO configuration from FSP
Set GpioOverride UPD to 1 to skip GPIO configuration in FSP phases
TEST=Able to build and boot ADLRVP to OS.
Change-Id: Ie965a85d9da9b6a23b385536313b852e66909cf4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 38c1a1b279..868d75e9da 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -157,6 +157,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev); m_cfg->TmeEnable = CONFIG(INTEL_TME); + + /* Skip GPIO configuration from FSP */ + m_cfg->GpioOverride = 0x1; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |