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authorAaron Durbin <adurbin@chromium.org>2016-04-11 15:01:58 -0500
committerAaron Durbin <adurbin@chromium.org>2016-04-13 16:07:51 +0200
commit108cd0e16d072bef918a3edac2a0e2703f47daba (patch)
treeff2729a19d158278dd4a96c8986ba07a191debe6 /src/soc/intel
parentff7670915c55cfddff144e3f2d78425e0042b52a (diff)
soc/intel/apollolake: logically group PMC BAR programming
The ACPI base address was being programmed sepearately from the other BARs in the PMC device. Group all the programming together so there isn't separate paths for programming the relevant BARs. Change-Id: Ib17684397fc19c42b39d066f981c01a886d65235 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14320 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/romstage.c15
1 files changed, 4 insertions, 11 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 4e800f7a2c..a277118b81 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -46,13 +46,12 @@ static void soc_early_romstage_init(void)
/* Set MCH base address and enable bit */
pci_write_config32(NB_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1);
- /* Set PMC base address */
+ /* Set PMC base addresses and enable decoding. */
pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0);
pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */
pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1);
pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */
-
- /* PMIO BAR4 was already set earlier, hence the COMMAND_IO below */
+ pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
pci_write_config32(pmc, PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER);
@@ -64,12 +63,6 @@ static void soc_early_romstage_init(void)
static void disable_watchdog(void)
{
uint32_t reg;
- device_t dev = PMC_DEV;
-
- /* Open up an IO window */
- pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
- pci_write_config32(dev, PCI_COMMAND,
- PCI_COMMAND_MASTER | PCI_COMMAND_IO);
/* Stop TCO timer */
reg = inl(ACPI_PMIO_BASE + 0x68);
@@ -86,10 +79,10 @@ asmlinkage void car_stage_entry(void)
printk(BIOS_DEBUG, "Starting romstage...\n");
- disable_watchdog();
-
soc_early_romstage_init();
+ disable_watchdog();
+
/* Make sure the blob does not override our data in CAR */
range_entry_init(&reg_car, (uintptr_t)_car_relocatable_data_end,
(uintptr_t)_car_region_end, 0);