diff options
| author | Jonathan Zhang <jonzhang@meta.com> | 2023-01-30 13:24:43 -0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-03-19 00:51:46 +0000 |
| commit | b94cc7d3672fd1756ae252c6505da716343a3c41 (patch) | |
| tree | 7863856717f498ff708625c229b2a7892cb0c9f1 /src/soc/intel/xeon_sp | |
| parent | 41ed2cb20e30862992837fb7dc62bc3cff2e457d (diff) | |
soc/intel/xeon_sp: Add P2SB definition for SPR-SP
Change-Id: I2ece7aac4339266068d4fc8fb1c58d0573eb2895
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/p2sb.h | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/p2sb.h b/src/soc/intel/xeon_sp/include/soc/p2sb.h index 3bdd4530ca..1be1b9b74d 100644 --- a/src/soc/intel/xeon_sp/include/soc/p2sb.h +++ b/src/soc/intel/xeon_sp/include/soc/p2sb.h @@ -3,14 +3,18 @@ #include <commonlib/helpers.h> /* - * Currently all known xeon-sp CPUs use C620 PCH. These definitions - * come from C620 datasheet (Intel Doc #336067-007US) + * CPX-SP and SKX-SP use LBG PCH, while SPR-SP uses EBG PCH. + * These definitions come from LBG datasheet (Intel Doc #336067-007US) + * and Emmitsburg datasheet (Intel Doc #606161). */ #define HPTC_OFFSET 0x60 #define HPTC_ADDR_ENABLE_BIT (1 << 7) -#define PCH_P2SB_EPMASK0 0xb0 #define P2SB_SIZE (16 * MiB) - #define P2SBC 0xe0 #define SBILOCK (1 << 31) +#if CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP) +#define PCH_P2SB_EPMASK0 0x220 +#else +#define PCH_P2SB_EPMASK0 0xb0 +#endif |