diff options
| author | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2023-06-13 10:21:58 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-15 15:08:12 +0000 |
| commit | b15946d72cbf98157ecf5062f5d610f821c0284e (patch) | |
| tree | 016d0409d4584979802442fc5c24e897377975fc /src/soc/intel/xeon_sp | |
| parent | 0acb78b21ff532ebc77b641cb80e5572fc84e0fe (diff) | |
soc/intel: Add max memory speed into dimm info
Add MaximumMemoryClockSpeed if FSP have it, otherwise pass 0.
TEST=check dmidecode dump the max speed.
Handle 0x000C, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 64 bits
Data Width: 64 bits
Size: 16 GB
Form Factor: SODIMM
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: DDR5
Type Detail: Unknown Synchronous
Speed: 5600 MT/s
Manufacturer: Micron
Serial Number: 3f064d84
Asset Tag: Channel-0-DIMM-0-AssetTag
Part Number: MTC8C1084S1SC56BG1
Rank: 1
Configured Memory Speed: 5200 MT/s
Minimum Voltage: 1.1 V
Maximum Voltage: 1.1 V
Configured Voltage: 1.1 V
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I854474bce8d6ed02f47f6dce8585b3ddfae73f80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75810
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/romstage.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/romstage.c | 7 |
2 files changed, 5 insertions, 8 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 265ab70d6d..fe2ca8654a 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -81,9 +81,6 @@ void save_dimm_info(void) return; } dest_dimm = &mem_info->dimm[index]; - dest_dimm->max_speed_mts = - get_max_memory_speed(src_dimm.commonTck); - dest_dimm->configured_speed_mts = hob->memFreq; dimm_info_fill(dest_dimm, src_dimm.DimmSize << 6, 0x1a, /* hard-coded memory device type as DDR4 */ @@ -99,7 +96,8 @@ void save_dimm_info(void) true, /* hard-coded as ECC supported */ src_dimm.VendorID, src_dimm.actKeyByte2, - 0); + 0, + get_max_memory_speed(src_dimm.commonTck)); index++; num_dimms++; } else if (mainboard_dimm_slot_exists(0, ch, dimm)) { diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index fef4d94d0f..8004730c59 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -304,9 +304,7 @@ void save_dimm_info(void) the board. */ continue; } - dest_dimm->max_speed_mts = - get_max_memory_speed(src_dimm.commonTck); - dest_dimm->configured_speed_mts = hob->memFreq; + dest_dimm->soc_num = soc; if (hob->DramType == SPD_TYPE_DDR5) { @@ -328,7 +326,8 @@ void save_dimm_info(void) sizeof(src_dimm.PartNumber), (const uint8_t *)&src_dimm.serialNumber[0], data_width, vdd_voltage, true, /* hard-coded as ECC supported */ - src_dimm.VendorID, src_dimm.actKeyByte2, 0); + src_dimm.VendorID, src_dimm.actKeyByte2, 0, + get_max_memory_speed(src_dimm.commonTck)); dimm_num++; } } |