diff options
| author | Tim Chu <Tim.Chu@quantatw.com> | 2022-12-13 12:11:45 +0000 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-03-19 09:53:41 +0000 |
| commit | 84fe84da84be118b2758081cc6abbb31f8f3409c (patch) | |
| tree | 72d075d2d5e202ee63e1c57d928e31128ccdb69f /src/soc/intel/xeon_sp | |
| parent | 3ed903fda9cb9b7237067f301d1efdb297a05a24 (diff) | |
soc/intel/xeon_sp/Makefile.inc: Build EBG for SPR-SP
Intel SPR-SP chipset has EBG instead of LBG.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I9429fe332bb5f01a41aa205c76ad9f0159f93eee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71959
Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com>
Reviewed-by: TimLiu-SMCI <timliu@supermicro.com.tw>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp')
| -rw-r--r-- | src/soc/intel/xeon_sp/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 4fb9b8e293..69792c486c 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -4,6 +4,7 @@ ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y) subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx lbg subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx lbg +subdirs-$(CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP) += spr ebg bootblock-y += bootblock.c spi.c lpc.c pch.c romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c |