diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-01-31 21:55:51 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-02-04 12:23:39 +0000 |
| commit | 526cc3ed44aacdad7a03ba7009baebbca2a308e8 (patch) | |
| tree | d9d8ad6ba02787fe70e4d12cd3e99aac5b8360c5 /src/soc/intel/xeon_sp | |
| parent | ebd75315b47619895725878682f84d0ae120e2c2 (diff) | |
soc/intel/{adl, common}: Add routines into CSE IA-common code
This patch adds routines to keep CSE and other HECI devices into the
lower power device state (AKA D0I3).
- cse_set_to_d0i3 => Set CSE device state to D0I3
- heci_set_to_d0i3 => Function sets D0I3 for all HECI devices
Additionally, creates a config `MAX_HECI_DEVICES` to pass the HECI
device count info from SoC layer to common CSE block.
As per PCH EDS, the HECI device count for various SoCs are:
ADL/CNL/EHL/ICL/JSL/TGL => 6 (CSE, IDE-R, KT, CSE2, CSE3 and CSE4)
APL => 1 (CSE)
SKL/Xeon_SP => 5 (CSE, IDE-R, KT, CSE2 and CSE3)
BUG=b:211954778
TEST=Able to build and boot Brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/xeon_sp')
| -rw-r--r-- | src/soc/intel/xeon_sp/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 0f025ac99e..32c2380216 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -75,6 +75,10 @@ config MAX_SOCKET int default 2 +config MAX_HECI_DEVICES + int + default 5 + # For 2S config, the number of cpus could be as high as # 2 threads * 20 cores * 2 sockets config MAX_CPUS |