diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-10-04 16:59:49 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-10-13 18:05:05 +0000 |
| commit | 2353cd9936702c6e556a9f810f180eced1e113d9 (patch) | |
| tree | 6b753a7a60bd1bcca7439287e63569f8a352ce05 /src/soc/intel/xeon_sp | |
| parent | 51254ee9397a535f5e51d9b12702b1a385e40f0e (diff) | |
soc/intel: drop P_BLK support
P_BLK is legacy and superseded by ACPI _CST. Also, the implementation
for most platforms in soc/intel is broken. Thus, drop it.
For APL the IO redirection is kept since it's used as replacement for
the broken MWAIT instructions.
Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/xeon_sp')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/msr.h | 9 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/skx/cpu.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/skx/soc_acpi.c | 5 |
3 files changed, 1 insertions, 20 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/msr.h b/src/soc/intel/xeon_sp/include/soc/msr.h index 3d68bf2565..9a8b641b49 100644 --- a/src/soc/intel/xeon_sp/include/soc/msr.h +++ b/src/soc/intel/xeon_sp/include/soc/msr.h @@ -28,18 +28,9 @@ /* No package C-state limit. All C-States supported by the processor are available. */ #define PKG_CSTATE_LIMIT_MASK (0xf << PKG_CSTATE_LIMIT_SHIFT) #define PKG_CSTATE_NO_LIMIT (0x7 << PKG_CSTATE_LIMIT_SHIFT) -#define IO_MWAIT_REDIRECTION_SHIFT 10 -#define IO_MWAIT_REDIRECTION_ENABLE (1 << IO_MWAIT_REDIRECTION_SHIFT) #define CFG_LOCK_SHIFT 15 #define CFG_LOCK_ENABLE (1 << CFG_LOCK_SHIFT) -/* MSR_PMG_IO_CAPTURE_BASE bits */ -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 -#define LVL_2_BASE_ADDRESS_SHIFT 0 /* 15:0 bits */ -#define LVL_2_BASE_ADDRESS (0x0514 << LVL_2_BASE_ADDRESS_SHIFT) -#define CST_RANGE_SHIFT 16 /* 18:16 bits */ -#define CST_RANGE_MAX_C6 (0x1 << CST_RANGE_SHIFT) - /* MSR_POWER_CTL bits */ #define MSR_POWER_CTL 0x1fc #define BIDIR_PROCHOT_ENABLE_SHIFT 0 diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index 848c907e58..df2b9b3a00 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -54,14 +54,9 @@ static void xeon_sp_core_init(struct device *cpu) /* set MSR_PKG_CST_CONFIG_CONTROL - scope per core*/ msr.hi = 0; - msr.lo = (PKG_CSTATE_NO_LIMIT | IO_MWAIT_REDIRECTION_ENABLE | CFG_LOCK_ENABLE); + msr.lo = (PKG_CSTATE_NO_LIMIT | CFG_LOCK_ENABLE); wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); - /* set MSR_PMG_IO_CAPTURE_BASE - scope per core */ - msr.hi = 0; - msr.lo = (LVL_2_BASE_ADDRESS | CST_RANGE_MAX_C6); - wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr); - /* Enable Energy Perf Bias Access, Dynamic switching and lock MSR */ msr = rdmsr(MSR_POWER_CTL); msr.lo |= (ENERGY_PERF_BIAS_ACCESS_ENABLE | PWR_PERF_TUNING_DYN_SWITCHING_ENABLE diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 41039eabdd..23bb6d6e3c 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -48,11 +48,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - - fadt->duty_width = 0; - /* RTC Registers */ fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |