diff options
| author | Jonathan Zhang <jonzhang@meta.com> | 2023-01-30 11:23:04 -0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-03-22 12:06:39 +0000 |
| commit | 09d2c93c72a80ba4480c62ab710000172348665e (patch) | |
| tree | 777e8384df58755a38273261003dfd47ffdf93bf /src/soc/intel/xeon_sp | |
| parent | a0b199c6b4836d1c8f11c2f87e98a5386b69b50f (diff) | |
soc/intel/xeon_sp/uncore.c: Add NCMEM base/limit to map entries
... instead of ME base/limit if the processor is configured with
SOC_INTEL_HAS_NCMEM.
Change-Id: I95783cad1a2d5a3599d120ea0c98e2aa8703bdb4
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72615
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/xeon_sp')
| -rw-r--r-- | src/soc/intel/xeon_sp/uncore.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 8729cf2540..9507253c62 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -29,6 +29,9 @@ enum { MMCFG_BASE_REG, MMCFG_LIMIT_REG, TOLM_REG, + /* NCMEM and ME ranges are mutually exclusive */ + NCMEM_BASE_REG, + NCMEM_LIMIT_REG, ME_BASE_REG, ME_LIMIT_REG, TSEG_BASE_REG, @@ -43,8 +46,13 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [MMCFG_BASE_REG] = MAP_ENTRY_BASE_64(VTD_MMCFG_BASE_CSR, "MMCFG_BASE"), [MMCFG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(VTD_MMCFG_LIMIT_CSR, 26, "MMCFG_LIMIT"), [TOLM_REG] = MAP_ENTRY_LIMIT_32(VTD_TOLM_CSR, 26, "TOLM"), +#if CONFIG(SOC_INTEL_HAS_NCMEM) + [NCMEM_BASE_REG] = MAP_ENTRY_BASE_64(VTD_NCMEM_BASE_CSR, "NCMEM_BASE"), + [NCMEM_LIMIT_REG] = MAP_ENTRY_LIMIT_64(VTD_NCMEM_LIMIT_CSR, 19, "NCMEM_LIMIT"), +#else [ME_BASE_REG] = MAP_ENTRY_BASE_64(VTD_ME_BASE_CSR, "ME_BASE"), [ME_LIMIT_REG] = MAP_ENTRY_LIMIT_64(VTD_ME_LIMIT_CSR, 19, "ME_LIMIT"), +#endif [TSEG_BASE_REG] = MAP_ENTRY_BASE_32(VTD_TSEG_BASE_CSR, "TSEGMB_BASE"), [TSEG_LIMIT_REG] = MAP_ENTRY_LIMIT_32(VTD_TSEG_LIMIT_CSR, 20, "TSEGMB_LIMIT"), }; |