diff options
| author | Jonathan Zhang <jonzhang@fb.com> | 2020-08-05 20:26:55 -0700 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-08 20:13:37 +0000 |
| commit | 7a1ebf9b8f44adaba89c0d95890b64ecd8fc7399 (patch) | |
| tree | 53e5bd4511fc1ed50d1fa3332842ad4aac50b0d3 /src/soc/intel/xeon_sp | |
| parent | ca55343b76cda66d5be1dea9eb2be3fbee901ea7 (diff) | |
vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc
Intel CPX-SP ww32 release has a number of bug fixes:
a. It fixed the issue related to some PCIe ports being hidden. This
affected DeltaLake config A, made the onboard PCIe NIC device not
working. ww32 release added two UPD parameters: PEXPHIDE, HidePEXPMenu.
b. It fixed the regression related to MRC cache.
c. It fixed the issue related to VT-d support, and added X2apic UPD
paramter. A separate PR will be submitted to enable VT-d in coreboot.
d. It fixed the issue related to enabling thermal device with PCI
or ACPI mode. [CB:44075] was submitted to enable it in coreboot.
e. It fixed the issue of FSP log level change UPD parameter DebugPrintLevel
not working.
There is a change in IIO UDS Hob.
TESTED=booted YV3 config A, and rebooted it. Access the target OS
remotely.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/romstage.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 7093ec9463..96949fd8af 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -57,5 +57,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) /* Needed to avoid FSP-M reset. The default value of 0x01 is for MinPlatform */ m_cfg->PchAdrEn = 0x02; + /* Make all IIO PCIe ports and port menus visible */ + m_cfg->PEXPHIDE = 0x0; + m_cfg->HidePEXPMenu = 0x0; + mainboard_memory_init_params(mupd); } |