diff options
| author | Jonathan Zhang <jonzhang@fb.com> | 2020-10-01 14:20:41 -0700 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-08 12:04:45 +0000 |
| commit | 407d552e0c642da601a88283676ee885402e81c4 (patch) | |
| tree | eeef89028fa15250d0bba3f24a0384d4813573cb /src/soc/intel/xeon_sp | |
| parent | 86b3bf10e60c137b01b81a37ce9827757f6af42d (diff) | |
vc/intel/fsp/fsp2_0/CPX-SP: update to Intel ww40 release
Intel CPX-SP FSP ww40 release adds MeUmaEnable FSP-M parameter,
and adds some fields to HOBs.
Update FspmUpd.h and HOB header files.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I3d456be62a5feecdac267c1e8be52e2a25e8aac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45940
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp')
0 files changed, 0 insertions, 0 deletions