diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-03-25 15:59:49 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2021-03-30 11:46:23 +0000 |
| commit | 83a55930ddedb38c603383a799ea3f40034b6df1 (patch) | |
| tree | 067aa3d9e70c275b9ade50f2735b25be3acc594d /src/soc/intel/xeon_sp | |
| parent | 6362df3f5ef6ebe4e1228962bcd09273cd57ce57 (diff) | |
soc/intel/xeon_sp: Prepare for CBnT BPM generation
To generate a working BPM, boot policy manifest for Intel CBnT the
tool that generates it, requires ACPI base and PCH PWRM base as input.
Therefore make it a Kconfig symbol, that can be used in Makefile.inc.
Change-Id: I6f1f9b53e34114682bd3258753f2d5aada9a530d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51805
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp')
| -rw-r--r-- | src/soc/intel/xeon_sp/Kconfig | 12 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/iomap.h | 4 |
2 files changed, 14 insertions, 2 deletions
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 44028bead5..61ab75090b 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -82,6 +82,18 @@ config MAX_CPUS int default 80 +config INTEL_ACPI_BASE_ADDRESS + hex + default 0x500 + help + IO Address of ACPI. + +config INTEL_PCH_PWRM_BASE_ADDRESS + hex + default 0xfe000000 + help + PCH PWRM Base address. + config PCR_BASE_ADDRESS hex default 0xfd000000 diff --git a/src/soc/intel/xeon_sp/include/soc/iomap.h b/src/soc/intel/xeon_sp/include/soc/iomap.h index 2df5f8bfe1..ceaf271eb2 100644 --- a/src/soc/intel/xeon_sp/include/soc/iomap.h +++ b/src/soc/intel/xeon_sp/include/soc/iomap.h @@ -19,7 +19,7 @@ #define SPI_BASE_SIZE 0x1000 #define TCO_BASE_ADDRESS 0x400 -#define ACPI_BASE_ADDRESS 0x500 +#define ACPI_BASE_ADDRESS CONFIG_INTEL_ACPI_BASE_ADDRESS #define ACPI_BASE_SIZE 0x100 /* Video RAM */ @@ -31,7 +31,7 @@ #define HECI1_BASE_ADDRESS 0xfed1a000 -#define PCH_PWRM_BASE_ADDRESS 0xfe000000 +#define PCH_PWRM_BASE_ADDRESS CONFIG_INTEL_PCH_PWRM_BASE_ADDRESS #define PCH_PWRM_BASE_SIZE 0x10000 #define P2SB_BAR CONFIG_PCR_BASE_ADDRESS |