diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-05-31 16:10:05 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-16 04:18:36 +0000 |
| commit | 3838edeac672a7f61597e6d38e14c16a84329d60 (patch) | |
| tree | 8ca0f437e57a43d88375f9d5da5e5226c590d89e /src/soc/intel/xeon_sp | |
| parent | 8a18bd8500fee7c43e257d3dfd1cc3f7db82c88c (diff) | |
soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them
Move locking CPU MSRs during CPU init instead of using
CONFIG_PARALLEL_MP_AP_WORK functions.
The AES Lock enable bit caused CPU exception errors as this should not
run on HT siblings. The set_aesni_lock() function takes care of that.
Change-Id: I21598c3e9a153dce25a09b187ddf9cf6363039d3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55098
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/chip.c | 18 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/cpu.c | 12 |
2 files changed, 10 insertions, 20 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 9164b7cbe7..19bf2af7e5 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -14,7 +14,6 @@ #include <soc/acpi.h> #include <soc/chip_common.h> #include <soc/cpu.h> -#include <soc/msr.h> #include <soc/pch.h> #include <soc/ramstage.h> #include <soc/p2sb.h> @@ -144,22 +143,6 @@ static void set_pcu_locks(void) } -static void set_msr_locks(void *unused) -{ - /* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions */ - msr_t msr; - - /* Lock Turbo */ - msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO); - msr.lo |= (TURBO_ACTIVATION_RATIO_LOCK); - wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr); - - /* Lock AES enable */ - msr = rdmsr(MSR_FEATURE_CONFIG); - msr.lo |= FEATURE_CONFIG_LOCK; - wrmsr(MSR_FEATURE_CONFIG, msr); -} - static void set_imc_locks(void) { struct device *dev = 0; @@ -182,7 +165,6 @@ static void chip_final(void *data) /* LOCK PAM */ pci_or_config32(pcidev_path_on_root(PCI_DEVFN(0, 0)), 0x80, 1 << 0); - mp_run_on_all_cpus(set_msr_locks, NULL); set_pcu_locks(); set_imc_locks(); set_upi_locks(); diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 339bf09aa2..cfd9e5c153 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpigen.h> #include <acpi/acpi.h> +#include <acpi/acpigen.h> #include <assert.h> #include <console/console.h> #include <console/debug.h> @@ -19,9 +19,10 @@ #include <intelpch/lockdown.h> #include <soc/cpu.h> #include <soc/msr.h> +#include <soc/pci_devs.h> #include <soc/pm.h> -#include <soc/soc_util.h> #include <soc/smmrelocate.h> +#include <soc/soc_util.h> #include <soc/util.h> #include "chip.h" @@ -103,6 +104,13 @@ static void each_cpu_init(struct device *cpu) /* Enable Vmx */ set_vmx_and_lock(); + set_aesni_lock(); + + /* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions + Lock Turbo. Did FSP-S set this up??? */ + msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO); + msr.lo |= (TURBO_ACTIVATION_RATIO_LOCK); + wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr); } static struct device_operations cpu_dev_ops = { |