summaryrefslogtreecommitdiff
path: root/src/soc/intel/xeon_sp
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-03-16 13:02:34 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-04-30 06:49:04 +0000
commit2ad598f3db4ff379a32aea27f0efb5a2449a8191 (patch)
treec36c22d2b1552a4380b317387fc90e52947b331c /src/soc/intel/xeon_sp
parentbc441c72ce7739a5a4ef647e3331afe5fbddc86e (diff)
ACPI: Use acpigen for NVS OperationRegions
The intermediate base and length are not required in ASL. Change-Id: I0c72e2e4f7ec597adc16dbdec1fd7bbe4e41bfd6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51637 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp')
0 files changed, 0 insertions, 0 deletions