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authorMichał Żygowski <michal.zygowski@3mdeb.com>2023-07-05 12:12:25 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-08-09 13:38:20 +0000
commit204ffcb98d5594983aed047ec2430e0b6aa515a0 (patch)
treeb13a29dbd67c12a4c29f7b95d819ccb43a9d6edb /src/soc/intel/xeon_sp
parent4fcaccf5da602af93942fbf3175264a5e7388f06 (diff)
soc/intel/xeon_sp/ebg: Add periodic SMI bits definition
Change-Id: Ia906a115538964628958bb4b6e3de3aa71577cce Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76252 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp')
-rw-r--r--src/soc/intel/xeon_sp/ebg/include/soc/pmc.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/ebg/include/soc/pmc.h b/src/soc/intel/xeon_sp/ebg/include/soc/pmc.h
index 5f80503a61..4362ce5eff 100644
--- a/src/soc/intel/xeon_sp/ebg/include/soc/pmc.h
+++ b/src/soc/intel/xeon_sp/ebg/include/soc/pmc.h
@@ -14,6 +14,11 @@
#define SUS_PWR_FLR (1 << 16)
#define PWR_FLR (1 << 14)
#define HOST_RST_STS (1 << 9)
+#define PER_SMI_SEL_MASK (3 << 1)
+#define SMI_RATE_64S (0 << 1)
+#define SMI_RATE_32S (1 << 1)
+#define SMI_RATE_16S (2 << 1)
+#define SMI_RATE_8S (3 << 1)
#define SLEEP_AFTER_POWER_FAIL (1 << 0)
#define GEN_PMCON_B 0x1024
#define SLP_STR_POL_LOCK (1 << 18)