soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroring

Drop the old, redundant code for mirroring LPC registers to DMI and make
use of the new common code.

Select the new Kconfig option for LPC DMI mirroring by the option
SOC_INTEL_COMMON_PCH_BASE, which is selected by platforms starting with
SPT, except APL and Xeon-SP. For Xeon-SP, select DMI and the new Kconfig
directly.

APL, even though it's younger than SPT, does not need mirroring.

Test: Set LGMR address by calling `lpc_open_mmio_window` and check that
      both the PCI cfg and DMI LGMR register get written correctly.

Tested successfully on clevo/cml-u.

Change-Id: Ibd834f1474d986646bcebb754a17db97831a651f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

2 files changed, 2 insertions, 10 deletions

diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index a8cecc5700..fac66f7881 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -39,8 +39,10 @@ config	CPU_SPECIFIC_OPTIONS
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select SOC_INTEL_COMMON_BLOCK
 	select SOC_INTEL_COMMON_BLOCK_CPU
+	select SOC_INTEL_COMMON_BLOCK_DMI
 	select SOC_INTEL_COMMON_BLOCK_TIMER
 	select SOC_INTEL_COMMON_BLOCK_LPC
+	select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI
 	select SOC_INTEL_COMMON_BLOCK_RTC
 	select SOC_INTEL_COMMON_BLOCK_SPI
 	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c
index 268db92f9a..f0cb6db63d 100644
--- a/src/soc/intel/xeon_sp/lpc.c
+++ b/src/soc/intel/xeon_sp/lpc.c
@@ -3,7 +3,6 @@
 #include <console/console.h>
 #include <arch/ioapic.h>
 #include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
 #include <soc/iomap.h>
 #include <soc/pcr_ids.h>
 
@@ -19,15 +18,6 @@ void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
 	gen_io_dec[3] = config->gen4_dec;
 }
 
-void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
-{
-	/* Mirror these same settings in DMI PCR */
-	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
-	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
-	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
-	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
-}
-
 void lpc_soc_init(struct device *dev)
 {
 	printk(BIOS_SPEW, "pch: lpc_init\n");