soc/intel/xeon_sp: Move read_msr_ppin() to common util.c

Move CPX and SKX read_msr_ppin() to common util.c file.
Update drivers/ocp/smbios #include to match.

Change-Id: I4c4281d2d5ce679f5444a502fa88df04de9f2cd8
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 32 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c
index 77fc1e4941..66b9ef11c1 100644
--- a/src/soc/intel/xeon_sp/util.c
+++ b/src/soc/intel/xeon_sp/util.c
@@ -3,6 +3,7 @@
 #include <console/console.h>
 #include <device/pci.h>
 #include <soc/pci_devs.h>
+#include <soc/msr.h>
 #include <soc/util.h>
 
 void get_stack_busnos(uint32_t *bus)
@@ -53,3 +54,34 @@ void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus
 	if (bus3)
 		*bus3 = (bus >> 24) & 0xff;
 }
+
+msr_t read_msr_ppin(void)
+{
+	msr_t ppin = {0};
+	msr_t msr;
+
+	/* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	if ((msr.lo & MSR_PPIN_CAP) == 0) {
+		printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n");
+		return ppin;
+	}
+
+	/* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */
+	msr = rdmsr(MSR_PPIN_CTL);
+	if (msr.lo & MSR_PPIN_CTL_LOCK) {
+		printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n");
+		return ppin;
+	}
+
+	if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) {
+		/* Set MSR_PPIN_CTL ENABLE to 1 */
+		msr.lo |= MSR_PPIN_CTL_ENABLE;
+		wrmsr(MSR_PPIN_CTL, msr);
+	}
+	ppin = rdmsr(MSR_PPIN);
+	/* Set enable to 0 after reading MSR_PPIN */
+	msr.lo &= ~MSR_PPIN_CTL_ENABLE;
+	wrmsr(MSR_PPIN_CTL, msr);
+	return ppin;
+}