soc/intel: Add Intel Xeon Scalable Processor support

This patch adds support for Intel Xeon-SP.

This patch is developed and verified with Skylake Scalable
Processor, which is a processor in Xeon-SP family. The code
is expected to be reusable for future geneations of Xeon-SP
processors, and will be updated with smaller targeted
patches accordingly, to add support for additional Xeon-SP
processors, to add features, and to improve the code base.

The Skylake-SP FSP is based on FSP 2.0. The FSP is a
proof-of-concept build. The binary is not shared in public,
when this patch is upstreamed.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Tested-by: johnny_lin@wiwynn.com
Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

1 files changed, 80 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/upd_display.c b/src/soc/intel/xeon_sp/upd_display.c
new file mode 100644
index 0000000000..2ae34ed2b9
--- /dev/null
+++ b/src/soc/intel/xeon_sp/upd_display.c
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <console/console.h>
+#include <fsp/util.h>
+#include <lib.h>
+
+#define DUMP_UPD(old, new, field) \
+	fsp_display_upd_value(#field, sizeof(old->field), old->field, new->field)
+
+/* Display the UPD parameters for MemoryInit */
+void soc_display_fspm_upd_params(
+	const FSPM_UPD *fspm_old_upd,
+	const FSPM_UPD *fspm_new_upd)
+{
+	const FSP_M_CONFIG *new;
+	const FSP_M_CONFIG *old;
+
+	old = &fspm_old_upd->FspmConfig;
+	new = &fspm_new_upd->FspmConfig;
+
+	printk(BIOS_DEBUG, "UPD values for MemoryInit:\n");
+
+	DUMP_UPD(old, new, PcdFspMrcDebugPrintErrorLevel);
+	DUMP_UPD(old, new, PcdFspKtiDebugPrintErrorLevel);
+	DUMP_UPD(old, new, PcdHsuartDevice);
+
+	hexdump(fspm_new_upd, sizeof(*fspm_new_upd));
+}
+
+/* Display the UPD parameters for SiliconInit */
+void soc_display_fsps_upd_params(
+	const FSPS_UPD *fsps_old_upd,
+	const FSPS_UPD *fsps_new_upd)
+{
+	const FSPS_CONFIG *new;
+	const FSPS_CONFIG *old;
+
+	old = &fsps_old_upd->FspsConfig;
+	new = &fsps_new_upd->FspsConfig;
+
+	printk(BIOS_DEBUG, "UPD values for SiliconInit:\n");
+
+	DUMP_UPD(old, new, PcdBifurcationPcie0);
+	DUMP_UPD(old, new, PcdBifurcationPcie1);
+	DUMP_UPD(old, new, PcdActiveCoreCount);
+	DUMP_UPD(old, new, PcdCpuMicrocodePatchBase);
+	DUMP_UPD(old, new, PcdCpuMicrocodePatchSize);
+	DUMP_UPD(old, new, PcdEnablePcie0);
+	DUMP_UPD(old, new, PcdEnablePcie1);
+	DUMP_UPD(old, new, PcdEnableEmmc);
+	DUMP_UPD(old, new, PcdEnableGbE);
+	DUMP_UPD(old, new, PcdFiaMuxConfigRequestPtr);
+	DUMP_UPD(old, new, PcdPcieRootPort0DeEmphasis);
+	DUMP_UPD(old, new, PcdPcieRootPort1DeEmphasis);
+	DUMP_UPD(old, new, PcdPcieRootPort2DeEmphasis);
+	DUMP_UPD(old, new, PcdPcieRootPort3DeEmphasis);
+	DUMP_UPD(old, new, PcdPcieRootPort4DeEmphasis);
+	DUMP_UPD(old, new, PcdPcieRootPort5DeEmphasis);
+	DUMP_UPD(old, new, PcdPcieRootPort6DeEmphasis);
+	DUMP_UPD(old, new, PcdPcieRootPort7DeEmphasis);
+	DUMP_UPD(old, new, PcdEMMCDLLConfigPtr);
+
+	hexdump(fsps_new_upd, sizeof(*fsps_new_upd));
+}