diff options
| author | Shuo Liu <shuo.liu@intel.com> | 2024-05-15 04:32:08 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-06-28 11:27:34 +0000 |
| commit | 0a6f5188e80d888529e2067d02add19f65cb013c (patch) | |
| tree | 05b052963e295911fa67fc0b41169d0393317fb2 /src/soc/intel/xeon_sp/uncore_acpi.c | |
| parent | bcd247376633b0fb4f1dbfbf8c2e02d2c926adec (diff) | |
soc/intel/xeon_sp: Reserve MMIO range for VTd BAR dynamically
vtd_probe_bar_size is used to decide the BAR size.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ie45dd29e386cbfcb136ce2152aba2ec67757ee3c
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82431
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/uncore_acpi.c')
| -rw-r--r-- | src/soc/intel/xeon_sp/uncore_acpi.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index a0bbbff9e1..22f8b6fed0 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -272,12 +272,13 @@ static unsigned long acpi_create_drhd(unsigned long current, struct device *iomm printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " "Register Base Address: 0x%x\n", DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); - current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, - pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, + pcie_seg, reg_base, vtd_probe_bar_size(iommu)); } else { printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); - current += acpi_create_dmar_drhd_4k(current, 0, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base, + vtd_probe_bar_size(iommu)); } // Add PCH IOAPIC |