soc/intel/xeon_sp: Enable SMI handler

SMI handler was not installed for Xeon_sp platforms. This enables SMM
relocation and SMI handling.

TESTED:
- SMRR are correctly set
- The save state revision is correct (0x00030101)
- SMI's are properly generated and handled
- SMM MSR save state are not supported, so relocate SMM on all cores
in series
- Verified on OCP/Deltalake mainboard.

NOTE:
- Code for accessing a CPU save state is not working for SMMLOADERV2,
so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS
pointer are not supported.
- This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS
is broken and needs to be fixed separately. It is unknown if TCO is
supported. This might require a cleanup in the future.

Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46231
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 144 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/smmrelocate.c b/src/soc/intel/xeon_sp/smmrelocate.c
new file mode 100644
index 0000000000..a71a740955
--- /dev/null
+++ b/src/soc/intel/xeon_sp/smmrelocate.c
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <assert.h>
+#include <string.h>
+#include <cpu/x86/mp.h>
+#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/intel/smm_reloc.h>
+#include <console/console.h>
+#include <smp/node.h>
+#include <soc/msr.h>
+#include <soc/smmrelocate.h>
+
+static void fill_in_relocation_params(struct smm_relocation_params *params)
+{
+	uintptr_t tseg_base;
+	size_t tseg_size;
+
+	smm_region(&tseg_base, &tseg_size);
+
+	if (!IS_ALIGNED(tseg_base, tseg_size)) {
+		/*
+		 * Note SMRR2 is supported which might support base/size combinations.
+		 * For now it looks like FSP-M always uses aligned base/size, so let's
+		 * not care about that.
+		 */
+		printk(BIOS_WARNING,
+		       "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n");
+		return;
+	}
+
+	/* SMRR has 32-bits of valid address aligned to 4KiB. */
+	if (!IS_ALIGNED(tseg_size, 4 * KiB)) {
+		printk(BIOS_WARNING,
+		       "TSEG size not aligned to the minimum 4KiB! Not setting SMRR\n");
+		return;
+	}
+
+	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
+
+	params->smrr_base.lo = tseg_base | MTRR_TYPE_WRBACK;
+	params->smrr_base.hi = 0;
+	params->smrr_mask.lo = ~(tseg_size - 1) | MTRR_PHYS_MASK_VALID;
+	params->smrr_mask.hi = 0;
+}
+
+static void setup_ied_area(struct smm_relocation_params *params)
+{
+	char *ied_base;
+
+	const struct ied_header ied = {
+		.signature = "INTEL RSVD",
+		.size = params->ied_size,
+		.reserved = {0},
+	};
+
+	ied_base = (void *)params->ied_base;
+
+	printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base);
+	printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size);
+
+	/* Place IED header at IEDBASE. */
+	memcpy(ied_base, &ied, sizeof(ied));
+
+	assert(params->ied_size > 1 * MiB + 32 * KiB);
+
+	/* Zero out 32KiB at IEDBASE + 1MiB */
+	memset(ied_base + 1 * MiB, 0, 32 * KiB);
+}
+
+void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
+		  size_t *smm_save_state_size)
+{
+	fill_in_relocation_params(&smm_reloc_params);
+
+	smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
+
+	if (smm_reloc_params.ied_size)
+		setup_ied_area(&smm_reloc_params);
+
+	*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
+}
+
+static void update_save_state(int cpu, uintptr_t curr_smbase,
+				uintptr_t staggered_smbase,
+				struct smm_relocation_params *relo_params)
+{
+	u32 smbase;
+	u32 iedbase;
+	int apic_id;
+	em64t101_smm_state_save_area_t *save_state;
+	/*
+	 * The relocated handler runs with all CPUs concurrently. Therefore
+	 * stagger the entry points adjusting SMBASE downwards by save state
+	 * size * CPU num.
+	 */
+	smbase = staggered_smbase;
+	iedbase = relo_params->ied_base;
+
+	apic_id = cpuid_ebx(1) >> 24;
+	printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n apic_id=0x%x\n",
+		smbase, iedbase, apic_id);
+
+	save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state));
+
+	save_state->smbase = smbase;
+	save_state->iedbase = iedbase;
+}
+
+/*
+ * The relocation work is actually performed in SMM context, but the code
+ * resides in the ramstage module. This occurs by trampolining from the default
+ * SMRAM entry point to here.
+ */
+void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
+				uintptr_t staggered_smbase)
+{
+	msr_t mtrr_cap;
+	struct smm_relocation_params *relo_params = &smm_reloc_params;
+
+	printk(BIOS_DEBUG, "%s : CPU %d\n", __func__, cpu);
+
+	/* Make appropriate changes to the save state map. */
+	update_save_state(cpu, curr_smbase, staggered_smbase, relo_params);
+
+	/* Write SMRR MSRs based on indicated support. */
+	mtrr_cap = rdmsr(MTRR_CAP_MSR);
+	if (mtrr_cap.lo & SMRR_SUPPORTED)
+		write_smrr(relo_params);
+}
+
+void smm_initialize(void)
+{
+	/* Clear the SMM state in the southbridge. */
+	smm_southbridge_clear_state();
+	/* Run the relocation handler for on the BSP . */
+	smm_initiate_relocation();
+}
+
+void smm_relocate(void)
+{
+	/* Save states via MSR does not seem to be supported on CPX */
+	if (!boot_cpu())
+		smm_initiate_relocation();
+}