soc/intel/xeon_sp: Enable SMI handler

SMI handler was not installed for Xeon_sp platforms. This enables SMM
relocation and SMI handling.

TESTED:
- SMRR are correctly set
- The save state revision is correct (0x00030101)
- SMI's are properly generated and handled
- SMM MSR save state are not supported, so relocate SMM on all cores
in series
- Verified on OCP/Deltalake mainboard.

NOTE:
- Code for accessing a CPU save state is not working for SMMLOADERV2,
so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS
pointer are not supported.
- This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS
is broken and needs to be fixed separately. It is unknown if TCO is
supported. This might require a cleanup in the future.

Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46231
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 14 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/smihandler.c b/src/soc/intel/xeon_sp/smihandler.c
new file mode 100644
index 0000000000..db3b429e61
--- /dev/null
+++ b/src/soc/intel/xeon_sp/smihandler.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/smihandler.h>
+#include <soc/pm.h>
+#include <cpu/x86/smm.h>
+
+/* This is needed by common SMM code */
+const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+	[APM_STS_BIT] = smihandler_southbridge_apmc,
+	[PM1_STS_BIT] = smihandler_southbridge_pm1,
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
+	[TCO_STS_BIT] = smihandler_southbridge_tco,
+#endif
+};