diff options
| author | Marc Jones <marcjones@sysproconsulting.com> | 2020-10-19 16:08:27 -0600 |
|---|---|---|
| committer | Marc Jones <marc@marcjonesconsulting.com> | 2020-10-22 21:35:45 +0000 |
| commit | 3fc04842cbe22fa29ea416fe746a8ee986605118 (patch) | |
| tree | 26009b6d3b31f0d806f33b46476be9cf7ca72a61 /src/soc/intel/xeon_sp/skx/soc_acpi.c | |
| parent | 521a03f30331ff89f3ac8d94cad03b8443ebf4ff (diff) | |
soc/intel/xeon_sp/skx: Move skx specific FADT setting
Prepare for common ACPI. Move the skx specific FADT settings
from acpi.c to soc_acpi.c, soc_fill_fadt. This gets acpi_fill_fadt()
to match common/block/acpi.c.
Change-Id: I04873d13d822de514acbb58501171285bd5b020e
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/skx/soc_acpi.c')
| -rw-r--r-- | src/soc/intel/xeon_sp/skx/soc_acpi.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 56ed0ce17b..7462d72b7a 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -55,6 +55,48 @@ uint32_t soc_read_sci_irq_select(void) return pci_read_config32(dev, PMC_ACPI_CNT); } +void soc_fill_fadt(acpi_fadt_t *fadt) +{ + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + /* Fix flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ + fadt->flags &= ~(ACPI_FADT_SEALED_CASE); + fadt->flags |= ACPI_FADT_SLEEP_TYPE; + + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + + fadt->duty_width = 0; + + /* RTC Registers */ + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + /* PM2 Control Registers */ + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x00; + + /* PM1 Timer Register */ + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x00; + +} + void uncore_inject_dsdt(const struct device *device) { size_t hob_size; |