soc/intel/xeon_sp: Refactor code to allow for additional CPUs types

Refactor the code and split it into Xeon common and CPU-specific code.
Move most Skylake-SP code into skx/ and keep common code in the current
folder.

This is a preparation for future work that will enable next
generation server CPU.

TEST=Tested on OCP Tioga Pass. There does not seem to be degradation
of stability as far as I could tell.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 30 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c
new file mode 100644
index 0000000000..947930f906
--- /dev/null
+++ b/src/soc/intel/xeon_sp/skx/romstage.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <arch/romstage.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/x86/mtrr.h>
+#include <intelblocks/rtc.h>
+#include <soc/romstage.h>
+#include <soc/soc_util.h>
+
+#include "chip.h"
+
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
+{
+	const config_t *config = config_of_soc();
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+	mupd->FspmUpdVersion = FSP_UPD_VERSION;
+
+	// ErrorLevel - 0 (disable) to 8 (verbose)
+	m_cfg->PcdFspMrcDebugPrintErrorLevel = 0;
+	m_cfg->PcdFspKtiDebugPrintErrorLevel = 0;
+
+	mainboard_memory_init_params(mupd);
+
+	m_cfg->VTdConfig.VTdSupport = config->vtd_support;
+	m_cfg->VTdConfig.CoherencySupport = config->coherency_support;
+	m_cfg->VTdConfig.ATS = config->ats_support;
+}