diff options
author | Marc Jones <marcjones@sysproconsulting.com> | 2020-07-23 11:54:38 -0600 |
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committer | Marc Jones <marc@marcjonesconsulting.com> | 2020-10-03 03:34:52 +0000 |
commit | b0e8c7c43799109b2147a02ebd1210e88beafd64 (patch) | |
tree | 94ac37eaeda5ac2392b73ff1717568c5a8b19b69 /src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl | |
parent | 07e8cd53486785610848adab2de23285488f2dcf (diff) |
soc/intel/xeon_sp: Use common ASL code for xeon_sp
Move and use the common xeon_sp/cpx/acpi asl for skx/.
There were only minor whitespace differences between the directories.
Update the mainboards to build the moved files.
TiogaPass coreboot.rom checked with BUILD_TIMELESS.
Change-Id: I5058a3fe8d96075a266fb92f10707bb94308c85b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45217
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl')
-rw-r--r-- | src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl | 95 |
1 files changed, 0 insertions, 95 deletions
diff --git a/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl deleted file mode 100644 index b2a2ebf850..0000000000 --- a/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Refer to IntelĀ® C620 Series Chipset Platform Controller Hub EDS section 20.11 - * CONFIG_PCR_BASE_ADDRESS 0xfd000000 0x3100 - * (0xfd000000 | ((uint8_t)(0xC4) << 16) | (uint16_t)(0x3100) = 0xFDC43100 - * - * PIRQ routing control is in PCR ITSS region. - */ - -OperationRegion (ITSS, SystemMemory, PCR_ITSS_PIRQA_ROUT + - CONFIG_PCR_BASE_ADDRESS + (PID_ITSS << PCR_PORTID_SHIFT), 8) -Field (ITSS, ByteAcc, NoLock, Preserve) -{ - PIRA, 8, /* PIRQA Routing Control */ - PIRB, 8, /* PIRQB Routing Control */ - PIRC, 8, /* PIRQC Routing Control */ - PIRD, 8, /* PIRQD Routing Control */ - PIRE, 8, /* PIRQE Routing Control */ - PIRF, 8, /* PIRQF Routing Control */ - PIRG, 8, /* PIRQG Routing Control */ - PIRH, 8, /* PIRQH Routing Control */ -} - -Name (IREN, 0x80) /* Interrupt Routing Enable */ -Name (IREM, 0x0f) /* Interrupt Routing Mask */ - -Name (PRSA, ResourceTemplate () -{ - IRQ (Level, ActiveLow, Shared, ) - {3,4,5,6,7,10,11,12,14,15} -}) -Alias (PRSA, PRSB) -Name (PRSC, ResourceTemplate () -{ - IRQ (Level, ActiveLow, Shared, ) - {3,4,5,6,10,11,12,14,15} -}) -Alias (PRSC, PRSD) -Alias (PRSA, PRSE) -Alias (PRSA, PRSF) -Alias (PRSA, PRSG) -Alias (PRSA, PRSH) - -#define MAKE_LINK_DEV(id,uid) \ - Device (LNK##id) \ - { \ - Name (_HID, EISAID ("PNP0C0F")) \ - Name (_UID, ##uid) \ - Method (_PRS, 0, NotSerialized) \ - { \ - Return (PRS##id) \ - } \ - Method (_CRS, 0, Serialized) \ - { \ - Name (RTLA, ResourceTemplate () \ - { \ - IRQ (Level, ActiveLow, Shared) {} \ - }) \ - CreateWordField (RTLA, 1, IRQ0) \ - Store (Zero, IRQ0) \ - \ - /* Set the bit from PIRQ Routing Register */ \ - ShiftLeft (1, And (^^PIR##id, ^^IREM), IRQ0) \ - Return (RTLA) \ - } \ - Method (_SRS, 1, Serialized) \ - { \ - CreateWordField (Arg0, 1, IRQ0) \ - FindSetRightBit (IRQ0, Local0) \ - Decrement (Local0) \ - Store (Local0, ^^PIR##id) \ - } \ - Method (_STA, 0, Serialized) \ - { \ - If (And (^^PIR##id, ^^IREN)) { \ - Return (0x9) \ - } Else { \ - Return (0xb) \ - } \ - } \ - Method (_DIS, 0, Serialized) \ - { \ - Or (^^PIR##id, ^^IREN, ^^PIR##id) \ - } \ - } - -MAKE_LINK_DEV(A,1) -MAKE_LINK_DEV(B,2) -MAKE_LINK_DEV(C,3) -MAKE_LINK_DEV(D,4) -MAKE_LINK_DEV(E,5) -MAKE_LINK_DEV(F,6) -MAKE_LINK_DEV(G,7) -MAKE_LINK_DEV(H,8) |