soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17

For now only implement for one socket and some of the fields
are hard-coded for DDR4 including memory device type, data width
and ECC support.

Change-Id: I3cb72d18027d972140828970206834ff55b72022
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 2 insertions, 1 deletions

diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c
index a4853c064e..f3e32fd9ca 100644
--- a/src/soc/intel/xeon_sp/romstage.c
+++ b/src/soc/intel/xeon_sp/romstage.c
@@ -41,7 +41,7 @@ asmlinkage void car_stage_entry(void)
 
 	/* Cache the memory-mapped boot media. */
 	postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
-
+	save_dimm_info();
 	run_postcar_phase(&pcf);
 }
 
@@ -54,3 +54,4 @@ __weak void mainboard_rtc_failed(void)
 {
 
 }
+__weak void save_dimm_info(void) { }