diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-12-16 11:30:40 +0100 |
|---|---|---|
| committer | Marc Jones <marc@marcjonesconsulting.com> | 2020-12-16 14:58:44 +0000 |
| commit | 83463076033f30c2b0693b1f39a01cfb9c679cf9 (patch) | |
| tree | f879d5c9fe28c283ec8f6d9ea5459311609c15cf /src/soc/intel/xeon_sp/pch.c | |
| parent | c7b63edeb47963ae97aa3478d45aaa8f4fa0cdf0 (diff) | |
soc/intel/xeon_sp: Move DMICTL lock
On SKX FSP-M does not return if this is set too early.
Tested on OCP/Tiogapass, boots.
Change-Id: Ib8ef7bab36bfd4b62988768753d10b4d7b7d567f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48657
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/pch.c')
| -rw-r--r-- | src/soc/intel/xeon_sp/pch.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c index 44824ca651..d2496b12fe 100644 --- a/src/soc/intel/xeon_sp/pch.c +++ b/src/soc/intel/xeon_sp/pch.c @@ -40,9 +40,6 @@ static void soc_config_acpibase(void) reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1; pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); - - reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL); - pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK); } void bootblock_pch_init(void) @@ -69,3 +66,9 @@ void override_hpet_ioapic_bdf(void) p2sb_set_ioapic_bdf(ioapic_bdf); p2sb_set_hpet_bdf(hpet_bdf); } + +void pch_lock_dmictl(void) +{ + uint32_t reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL); + pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK); +} |