soc/intel/xeon_sp: Refactor code to allow for additional CPUs types

Refactor the code and split it into Xeon common and CPU-specific code.
Move most Skylake-SP code into skx/ and keep common code in the current
folder.

This is a preparation for future work that will enable next
generation server CPU.

TEST=Tested on OCP Tioga Pass. There does not seem to be degradation
of stability as far as I could tell.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 1 insertions, 2 deletions

diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c
index 6dc2c41fe0..c2f1f89181 100644
--- a/src/soc/intel/xeon_sp/lpc.c
+++ b/src/soc/intel/xeon_sp/lpc.c
@@ -17,11 +17,10 @@
 #include <arch/ioapic.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
-#include <soc/soc_util.h>
 #include <soc/iomap.h>
 #include <soc/pcr_ids.h>
 
-#include "chip.h"
+#include <chip.h>
 
 static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = {
 	{ 0, 0 }