soc/intel/xeon_sp: Refactor code to allow for additional CPUs types

Refactor the code and split it into Xeon common and CPU-specific code.
Move most Skylake-SP code into skx/ and keep common code in the current
folder.

This is a preparation for future work that will enable next
generation server CPU.

TEST=Tested on OCP Tioga Pass. There does not seem to be degradation
of stability as far as I could tell.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

9 files changed, 7 insertions, 780 deletions

diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h
deleted file mode 100644
index 8e1dcb8d0c..0000000000
--- a/src/soc/intel/xeon_sp/include/soc/acpi.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#ifndef _SOC_ACPI_H_
-#define _SOC_ACPI_H_
-
-#include <arch/acpi.h>
-#include <soc/nvs.h>
-
-#define MEM_BLK_COUNT      0x140
-typedef struct {
-	uint8_t   buf[32];
-} MEM_BLK;
-
-void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
-unsigned long acpi_madt_irq_overrides(unsigned long current);
-void acpi_init_gnvs(global_nvs_t *gnvs);
-unsigned long northbridge_write_acpi_tables(struct device *device,
-	unsigned long current, struct acpi_rsdp *rsdp);
-void uncore_inject_dsdt(void);
-void motherboard_fill_fadt(acpi_fadt_t *fadt);
-
-#endif /* _SOC_ACPI_H_ */
diff --git a/src/soc/intel/xeon_sp/include/soc/cpu.h b/src/soc/intel/xeon_sp/include/soc/cpu.h
deleted file mode 100644
index 611fb19715..0000000000
--- a/src/soc/intel/xeon_sp/include/soc/cpu.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_CPU_H_
-#define _SOC_CPU_H_
-
-#include <device/device.h>
-
-/* SKXSP CPUID */
-#define CPUID_SKYLAKE_SP_A0_A1 0x506f0
-#define CPUID_SKYLAKE_SP_B0 0x506f1
-#define CPUID_SKYLAKE_SP_4 0x50654
-
-/* CPU bus clock is fixed at 100MHz */
-#define CPU_BCLK 100
-
-int get_cpu_count(void);
-void xeon_sp_init_cpus(struct device *dev);
-
-#endif
diff --git a/src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h b/src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h
deleted file mode 100644
index ac230ef78b..0000000000
--- a/src/soc/intel/xeon_sp/include/soc/gpio_soc_defs.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _GPIO_SOC_DEFS_H_
-#define _GPIO_SOC_DEFS_H_
-
-///
-/// Skylake-SP chipset GPIO Groups
-///
-#define GPIO_SKL_H_GROUP_GPP_A  0x0100
-#define GPIO_SKL_H_GROUP_GPP_B  0x0101
-#define GPIO_SKL_H_GROUP_GPP_C  0x0102
-#define GPIO_SKL_H_GROUP_GPP_D  0x0103
-#define GPIO_SKL_H_GROUP_GPP_E  0x0104
-#define GPIO_SKL_H_GROUP_GPP_F  0x0105
-#define GPIO_SKL_H_GROUP_GPP_G  0x0106
-#define GPIO_SKL_H_GROUP_GPP_H  0x0107
-#define GPIO_SKL_H_GROUP_GPP_I  0x0108
-#define GPIO_SKL_H_GROUP_GPP_J  0x0109
-#define GPIO_SKL_H_GROUP_GPP_K  0x010A
-#define GPIO_SKL_H_GROUP_GPP_L  0x010B
-#define GPIO_SKL_H_GROUP_GPD    0x010C
-
-///
-/// SKL H GPIO pins
-///
-#define GPIO_SKL_H_GPP_A0       0x01000000
-#define GPIO_SKL_H_GPP_A1       0x01000001
-#define GPIO_SKL_H_GPP_A2       0x01000002
-#define GPIO_SKL_H_GPP_A3       0x01000003
-#define GPIO_SKL_H_GPP_A4       0x01000004
-#define GPIO_SKL_H_GPP_A5       0x01000005
-#define GPIO_SKL_H_GPP_A6       0x01000006
-#define GPIO_SKL_H_GPP_A7       0x01000007
-#define GPIO_SKL_H_GPP_A8       0x01000008
-#define GPIO_SKL_H_GPP_A9       0x01000009
-#define GPIO_SKL_H_GPP_A10      0x0100000A
-#define GPIO_SKL_H_GPP_A11      0x0100000B
-#define GPIO_SKL_H_GPP_A12      0x0100000C
-#define GPIO_SKL_H_GPP_A13      0x0100000D
-#define GPIO_SKL_H_GPP_A14      0x0100000E
-#define GPIO_SKL_H_GPP_A15      0x0100000F
-#define GPIO_SKL_H_GPP_A16      0x01000010
-#define GPIO_SKL_H_GPP_A17      0x01000011
-#define GPIO_SKL_H_GPP_A18      0x01000012
-#define GPIO_SKL_H_GPP_A19      0x01000013
-#define GPIO_SKL_H_GPP_A20      0x01000014
-#define GPIO_SKL_H_GPP_A21      0x01000015
-#define GPIO_SKL_H_GPP_A22      0x01000016
-#define GPIO_SKL_H_GPP_A23      0x01000017
-#define GPIO_SKL_H_GPP_B0       0x01010000
-#define GPIO_SKL_H_GPP_B1       0x01010001
-#define GPIO_SKL_H_GPP_B2       0x01010002
-#define GPIO_SKL_H_GPP_B3       0x01010003
-#define GPIO_SKL_H_GPP_B4       0x01010004
-#define GPIO_SKL_H_GPP_B5       0x01010005
-#define GPIO_SKL_H_GPP_B6       0x01010006
-#define GPIO_SKL_H_GPP_B7       0x01010007
-#define GPIO_SKL_H_GPP_B8       0x01010008
-#define GPIO_SKL_H_GPP_B9       0x01010009
-#define GPIO_SKL_H_GPP_B10      0x0101000A
-#define GPIO_SKL_H_GPP_B11      0x0101000B
-#define GPIO_SKL_H_GPP_B12      0x0101000C
-#define GPIO_SKL_H_GPP_B13      0x0101000D
-#define GPIO_SKL_H_GPP_B14      0x0101000E
-#define GPIO_SKL_H_GPP_B15      0x0101000F
-#define GPIO_SKL_H_GPP_B16      0x01010010
-#define GPIO_SKL_H_GPP_B17      0x01010011
-#define GPIO_SKL_H_GPP_B18      0x01010012
-#define GPIO_SKL_H_GPP_B19      0x01010013
-#define GPIO_SKL_H_GPP_B20      0x01010014
-#define GPIO_SKL_H_GPP_B21      0x01010015
-#define GPIO_SKL_H_GPP_B22      0x01010016
-#define GPIO_SKL_H_GPP_B23      0x01010017
-#define GPIO_SKL_H_GPP_C0       0x01020000
-#define GPIO_SKL_H_GPP_C1       0x01020001
-#define GPIO_SKL_H_GPP_C2       0x01020002
-#define GPIO_SKL_H_GPP_C3       0x01020003
-#define GPIO_SKL_H_GPP_C4       0x01020004
-#define GPIO_SKL_H_GPP_C5       0x01020005
-#define GPIO_SKL_H_GPP_C6       0x01020006
-#define GPIO_SKL_H_GPP_C7       0x01020007
-#define GPIO_SKL_H_GPP_C8       0x01020008
-#define GPIO_SKL_H_GPP_C9       0x01020009
-#define GPIO_SKL_H_GPP_C10      0x0102000A
-#define GPIO_SKL_H_GPP_C11      0x0102000B
-#define GPIO_SKL_H_GPP_C12      0x0102000C
-#define GPIO_SKL_H_GPP_C13      0x0102000D
-#define GPIO_SKL_H_GPP_C14      0x0102000E
-#define GPIO_SKL_H_GPP_C15      0x0102000F
-#define GPIO_SKL_H_GPP_C16      0x01020010
-#define GPIO_SKL_H_GPP_C17      0x01020011
-#define GPIO_SKL_H_GPP_C18      0x01020012
-#define GPIO_SKL_H_GPP_C19      0x01020013
-#define GPIO_SKL_H_GPP_C20      0x01020014
-#define GPIO_SKL_H_GPP_C21      0x01020015
-#define GPIO_SKL_H_GPP_C22      0x01020016
-#define GPIO_SKL_H_GPP_C23      0x01020017
-#define GPIO_SKL_H_GPP_D0       0x01030000
-#define GPIO_SKL_H_GPP_D1       0x01030001
-#define GPIO_SKL_H_GPP_D2       0x01030002
-#define GPIO_SKL_H_GPP_D3       0x01030003
-#define GPIO_SKL_H_GPP_D4       0x01030004
-#define GPIO_SKL_H_GPP_D5       0x01030005
-#define GPIO_SKL_H_GPP_D6       0x01030006
-#define GPIO_SKL_H_GPP_D7       0x01030007
-#define GPIO_SKL_H_GPP_D8       0x01030008
-#define GPIO_SKL_H_GPP_D9       0x01030009
-#define GPIO_SKL_H_GPP_D10      0x0103000A
-#define GPIO_SKL_H_GPP_D11      0x0103000B
-#define GPIO_SKL_H_GPP_D12      0x0103000C
-#define GPIO_SKL_H_GPP_D13      0x0103000D
-#define GPIO_SKL_H_GPP_D14      0x0103000E
-#define GPIO_SKL_H_GPP_D15      0x0103000F
-#define GPIO_SKL_H_GPP_D16      0x01030010
-#define GPIO_SKL_H_GPP_D17      0x01030011
-#define GPIO_SKL_H_GPP_D18      0x01030012
-#define GPIO_SKL_H_GPP_D19      0x01030013
-#define GPIO_SKL_H_GPP_D20      0x01030014
-#define GPIO_SKL_H_GPP_D21      0x01030015
-#define GPIO_SKL_H_GPP_D22      0x01030016
-#define GPIO_SKL_H_GPP_D23      0x01030017
-#define GPIO_SKL_H_GPP_E0       0x01040000
-#define GPIO_SKL_H_GPP_E1       0x01040001
-#define GPIO_SKL_H_GPP_E2       0x01040002
-#define GPIO_SKL_H_GPP_E3       0x01040003
-#define GPIO_SKL_H_GPP_E4       0x01040004
-#define GPIO_SKL_H_GPP_E5       0x01040005
-#define GPIO_SKL_H_GPP_E6       0x01040006
-#define GPIO_SKL_H_GPP_E7       0x01040007
-#define GPIO_SKL_H_GPP_E8       0x01040008
-#define GPIO_SKL_H_GPP_E9       0x01040009
-#define GPIO_SKL_H_GPP_E10      0x0104000A
-#define GPIO_SKL_H_GPP_E11      0x0104000B
-#define GPIO_SKL_H_GPP_E12      0x0104000C
-#define GPIO_SKL_H_GPP_F0       0x01050000
-#define GPIO_SKL_H_GPP_F1       0x01050001
-#define GPIO_SKL_H_GPP_F2       0x01050002
-#define GPIO_SKL_H_GPP_F3       0x01050003
-#define GPIO_SKL_H_GPP_F4       0x01050004
-#define GPIO_SKL_H_GPP_F5       0x01050005
-#define GPIO_SKL_H_GPP_F6       0x01050006
-#define GPIO_SKL_H_GPP_F7       0x01050007
-#define GPIO_SKL_H_GPP_F8       0x01050008
-#define GPIO_SKL_H_GPP_F9       0x01050009
-#define GPIO_SKL_H_GPP_F10      0x0105000A
-#define GPIO_SKL_H_GPP_F11      0x0105000B
-#define GPIO_SKL_H_GPP_F12      0x0105000C
-#define GPIO_SKL_H_GPP_F13      0x0105000D
-#define GPIO_SKL_H_GPP_F14      0x0105000E
-#define GPIO_SKL_H_GPP_F15      0x0105000F
-#define GPIO_SKL_H_GPP_F16      0x01050010
-#define GPIO_SKL_H_GPP_F17      0x01050011
-#define GPIO_SKL_H_GPP_F18      0x01050012
-#define GPIO_SKL_H_GPP_F19      0x01050013
-#define GPIO_SKL_H_GPP_F20      0x01050014
-#define GPIO_SKL_H_GPP_F21      0x01050015
-#define GPIO_SKL_H_GPP_F22      0x01050016
-#define GPIO_SKL_H_GPP_F23      0x01050017
-#define GPIO_SKL_H_GPP_G0       0x01060000
-#define GPIO_SKL_H_GPP_G1       0x01060001
-#define GPIO_SKL_H_GPP_G2       0x01060002
-#define GPIO_SKL_H_GPP_G3       0x01060003
-#define GPIO_SKL_H_GPP_G4       0x01060004
-#define GPIO_SKL_H_GPP_G5       0x01060005
-#define GPIO_SKL_H_GPP_G6       0x01060006
-#define GPIO_SKL_H_GPP_G7       0x01060007
-#define GPIO_SKL_H_GPP_G8       0x01060008
-#define GPIO_SKL_H_GPP_G9       0x01060009
-#define GPIO_SKL_H_GPP_G10      0x0106000A
-#define GPIO_SKL_H_GPP_G11      0x0106000B
-#define GPIO_SKL_H_GPP_G12      0x0106000C
-#define GPIO_SKL_H_GPP_G13      0x0106000D
-#define GPIO_SKL_H_GPP_G14      0x0106000E
-#define GPIO_SKL_H_GPP_G15      0x0106000F
-#define GPIO_SKL_H_GPP_G16      0x01060010
-#define GPIO_SKL_H_GPP_G17      0x01060011
-#define GPIO_SKL_H_GPP_G18      0x01060012
-#define GPIO_SKL_H_GPP_G19      0x01060013
-#define GPIO_SKL_H_GPP_G20      0x01060014
-#define GPIO_SKL_H_GPP_G21      0x01060015
-#define GPIO_SKL_H_GPP_G22      0x01060016
-#define GPIO_SKL_H_GPP_G23      0x01060017
-#define GPIO_SKL_H_GPP_H0       0x01070000
-#define GPIO_SKL_H_GPP_H1       0x01070001
-#define GPIO_SKL_H_GPP_H2       0x01070002
-#define GPIO_SKL_H_GPP_H3       0x01070003
-#define GPIO_SKL_H_GPP_H4       0x01070004
-#define GPIO_SKL_H_GPP_H5       0x01070005
-#define GPIO_SKL_H_GPP_H6       0x01070006
-#define GPIO_SKL_H_GPP_H7       0x01070007
-#define GPIO_SKL_H_GPP_H8       0x01070008
-#define GPIO_SKL_H_GPP_H9       0x01070009
-#define GPIO_SKL_H_GPP_H10      0x0107000A
-#define GPIO_SKL_H_GPP_H11      0x0107000B
-#define GPIO_SKL_H_GPP_H12      0x0107000C
-#define GPIO_SKL_H_GPP_H13      0x0107000D
-#define GPIO_SKL_H_GPP_H14      0x0107000E
-#define GPIO_SKL_H_GPP_H15      0x0107000F
-#define GPIO_SKL_H_GPP_H16      0x01070010
-#define GPIO_SKL_H_GPP_H17      0x01070011
-#define GPIO_SKL_H_GPP_H18      0x01070012
-#define GPIO_SKL_H_GPP_H19      0x01070013
-#define GPIO_SKL_H_GPP_H20      0x01070014
-#define GPIO_SKL_H_GPP_H21      0x01070015
-#define GPIO_SKL_H_GPP_H22      0x01070016
-#define GPIO_SKL_H_GPP_H23      0x01070017
-#define GPIO_SKL_H_GPP_I0       0x01080000
-#define GPIO_SKL_H_GPP_I1       0x01080001
-#define GPIO_SKL_H_GPP_I2       0x01080002
-#define GPIO_SKL_H_GPP_I3       0x01080003
-#define GPIO_SKL_H_GPP_I4       0x01080004
-#define GPIO_SKL_H_GPP_I5       0x01080005
-#define GPIO_SKL_H_GPP_I6       0x01080006
-#define GPIO_SKL_H_GPP_I7       0x01080007
-#define GPIO_SKL_H_GPP_I8       0x01080008
-#define GPIO_SKL_H_GPP_I9       0x01080009
-#define GPIO_SKL_H_GPP_I10      0x0108000A
-
-#define GPIO_SKL_H_GPP_J0       0x01090000
-#define GPIO_SKL_H_GPP_J1       0x01090001
-#define GPIO_SKL_H_GPP_J2       0x01090002
-#define GPIO_SKL_H_GPP_J3       0x01090003
-#define GPIO_SKL_H_GPP_J4       0x01090004
-#define GPIO_SKL_H_GPP_J5       0x01090005
-#define GPIO_SKL_H_GPP_J6       0x01090006
-#define GPIO_SKL_H_GPP_J7       0x01090007
-#define GPIO_SKL_H_GPP_J8       0x01090008
-#define GPIO_SKL_H_GPP_J9       0x01090009
-#define GPIO_SKL_H_GPP_J10      0x0109000A
-#define GPIO_SKL_H_GPP_J11      0x0109000B
-#define GPIO_SKL_H_GPP_J12      0x0109000C
-#define GPIO_SKL_H_GPP_J13      0x0109000D
-#define GPIO_SKL_H_GPP_J14      0x0109000E
-#define GPIO_SKL_H_GPP_J15      0x0109000F
-#define GPIO_SKL_H_GPP_J16      0x01090010
-#define GPIO_SKL_H_GPP_J17      0x01090011
-#define GPIO_SKL_H_GPP_J18      0x01090012
-#define GPIO_SKL_H_GPP_J19      0x01090013
-#define GPIO_SKL_H_GPP_J20      0x01090014
-#define GPIO_SKL_H_GPP_J21      0x01090015
-#define GPIO_SKL_H_GPP_J22      0x01090016
-#define GPIO_SKL_H_GPP_J23      0x01090017
-#define GPIO_SKL_H_GPP_K0       0x010A0000
-#define GPIO_SKL_H_GPP_K1       0x010A0001
-#define GPIO_SKL_H_GPP_K2       0x010A0002
-#define GPIO_SKL_H_GPP_K3       0x010A0003
-#define GPIO_SKL_H_GPP_K4       0x010A0004
-#define GPIO_SKL_H_GPP_K5       0x010A0005
-#define GPIO_SKL_H_GPP_K6       0x010A0006
-#define GPIO_SKL_H_GPP_K7       0x010A0007
-#define GPIO_SKL_H_GPP_K8       0x010A0008
-#define GPIO_SKL_H_GPP_K9       0x010A0009
-#define GPIO_SKL_H_GPP_K10      0x010A000A
-#define GPIO_SKL_H_GPP_L2       0x010B0002
-#define GPIO_SKL_H_GPP_L3       0x010B0003
-#define GPIO_SKL_H_GPP_L4       0x010B0004
-#define GPIO_SKL_H_GPP_L5       0x010B0005
-#define GPIO_SKL_H_GPP_L6       0x010B0006
-#define GPIO_SKL_H_GPP_L7       0x010B0007
-#define GPIO_SKL_H_GPP_L8       0x010B0008
-#define GPIO_SKL_H_GPP_L9       0x010B0009
-#define GPIO_SKL_H_GPP_L10      0x010B000A
-#define GPIO_SKL_H_GPP_L11      0x010B000B
-#define GPIO_SKL_H_GPP_L12      0x010B000C
-#define GPIO_SKL_H_GPP_L13      0x010B000D
-#define GPIO_SKL_H_GPP_L14      0x010B000E
-#define GPIO_SKL_H_GPP_L15      0x010B000F
-#define GPIO_SKL_H_GPP_L16      0x010B0010
-#define GPIO_SKL_H_GPP_L17      0x010B0011
-#define GPIO_SKL_H_GPP_L18      0x010B0012
-#define GPIO_SKL_H_GPP_L19      0x010B0013
-#define GPIO_SKL_H_GPD0         0x010C0000
-#define GPIO_SKL_H_GPD1         0x010C0001
-#define GPIO_SKL_H_GPD2         0x010C0002
-#define GPIO_SKL_H_GPD3         0x010C0003
-#define GPIO_SKL_H_GPD4         0x010C0004
-#define GPIO_SKL_H_GPD5         0x010C0005
-#define GPIO_SKL_H_GPD6         0x010C0006
-#define GPIO_SKL_H_GPD7         0x010C0007
-#define GPIO_SKL_H_GPD8         0x010C0008
-#define GPIO_SKL_H_GPD9         0x010C0009
-#define GPIO_SKL_H_GPD10        0x010C000A
-#define GPIO_SKL_H_GPD11        0x010C000B
-
-#endif
diff --git a/src/soc/intel/xeon_sp/include/soc/irq.h b/src/soc/intel/xeon_sp/include/soc/irq.h
deleted file mode 100644
index bfb800862f..0000000000
--- a/src/soc/intel/xeon_sp/include/soc/irq.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_IRQ_H_
-#define _SOC_IRQ_H_
-
-#define PCH_IRQ10          10
-#define PCH_IRQ11          11
-
-#endif /* _SOC_IRQ_H_ */
diff --git a/src/soc/intel/xeon_sp/include/soc/msr.h b/src/soc/intel/xeon_sp/include/soc/msr.h
deleted file mode 100644
index 95057769bb..0000000000
--- a/src/soc/intel/xeon_sp/include/soc/msr.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_MSR_H_
-#define _SOC_MSR_H_
-
-#include <intelblocks/msr.h>
-
-#define IA32_MCG_CAP                    0x179
-#define IA32_MCG_CAP_COUNT_MASK         0xff
-#define IA32_MCG_CAP_CTL_P_BIT          8
-#define IA32_MCG_CAP_CTL_P_MASK         (1 << IA32_MCG_CAP_CTL_P_BIT)
-
-#define IA32_MCG_CTL                    0x17b
-
-/* IA32_MISC_ENABLE bits */
-#define FAST_STRINGS_ENABLE_BIT         (1 << 0)
-#define SPEED_STEP_ENABLE_BIT           (1 << 16)
-#define MONIOR_ENABLE_BIT               (1 << 18)
-
-#define MSR_IA32_ENERGY_PERF_BIAS       0x1b0
-
-/* MSR_PKG_CST_CONFIG_CONTROL bits */
-#define MSR_PKG_CST_CONFIG_CONTROL       0xe2
-#define PKG_CSTATE_LIMIT_SHIFT           0 /* 0:3 */
-/* No package C-state limit. All C-States supported by the processor are available. */
-#define PKG_CSTATE_LIMIT_MASK            (0xf << PKG_CSTATE_LIMIT_SHIFT)
-#define PKG_CSTATE_NO_LIMIT              (0x7 << PKG_CSTATE_LIMIT_SHIFT)
-#define IO_MWAIT_REDIRECTION_SHIFT       10
-#define IO_MWAIT_REDIRECTION_ENABLE      (1 << IO_MWAIT_REDIRECTION_SHIFT)
-#define CFG_LOCK_SHIFT                   15
-#define CFG_LOCK_ENABLE                  (1 << CFG_LOCK_SHIFT)
-
-/* MSR_PMG_IO_CAPTURE_BASE bits */
-#define MSR_PMG_IO_CAPTURE_BASE          0xe4
-#define LVL_2_BASE_ADDRESS_SHIFT         0 /* 15:0 bits */
-#define LVL_2_BASE_ADDRESS               (0x0514 << LVL_2_BASE_ADDRESS_SHIFT)
-#define CST_RANGE_SHIFT                  16 /* 18:16 bits */
-#define CST_RANGE_MAX_C6                 (0x1 << CST_RANGE_SHIFT)
-
-/* MSR_POWER_CTL bits */
-#define MSR_POWER_CTL                            0x1fc
-#define BIDIR_PROCHOT_ENABLE_SHIFT               0
-#define BIDIR_PROCHOT_ENABLE                     (1 << BIDIR_PROCHOT_ENABLE_SHIFT)
-#define FAST_BRK_SNP_ENABLE_SHIFT                3
-#define FAST_BRK_SNP_ENABLE                      (1 << FAST_BRK_SNP_ENABLE_SHIFT)
-#define FAST_BRK_INT_ENABLE_SHIFT                4
-#define FAST_BRK_INT_ENABLE                      (1 << FAST_BRK_INT_ENABLE_SHIFT)
-#define PHOLD_CST_PREVENTION_INIT_SHIFT          6
-#define PHOLD_CST_PREVENTION_INIT_VALUE          (1 << PHOLD_CST_PREVENTION_INIT_SHIFT)
-#define ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT     18
-#define ENERGY_PERF_BIAS_ACCESS_ENABLE           (1 << ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT)
-#define PROCHOT_OUTPUT_DISABLE_SHIFT             21
-#define PROCHOT_OUTPUT_DISABLE                   (1 << PROCHOT_OUTPUT_DISABLE_SHIFT)
-#define PWR_PERF_TUNING_DYN_SWITCHING_SHIFT      24
-#define PWR_PERF_TUNING_DYN_SWITCHING_ENABLE     (1 << PWR_PERF_TUNING_DYN_SWITCHING_SHIFT)
-#define PROCHOT_LOCK_SHIFT                       27
-#define PROCHOT_LOCK_ENABLE                      (1 << PROCHOT_LOCK_SHIFT)
-#define LTR_IIO_DISABLE_SHIFT                    29
-#define LTR_IIO_DISABLE                          (1 << LTR_IIO_DISABLE_SHIFT)
-
-/* MSR_IA32_PERF_CTRL (0x199) bits */
-#define MSR_IA32_PERF_CTRL          0x199
-#define PSTATE_REQ_SHIFT            8 /* 8:14 bits */
-#define PSTATE_REQ_MASK             (0x7f << PSTATE_REQ_SHIFT)
-#define PSTATE_REQ_RATIO            (0xa << PSTATE_REQ_SHIFT)
-
-/* MSR_MISC_PWR_MGMT bits */
-#define MSR_MISC_PWR_MGMT            0x1aa
-#define HWP_ENUM_SHIFT               6
-#define HWP_ENUM_ENABLE              (1 << HWP_ENUM_SHIFT)
-#define HWP_EPP_SHIFT                12
-#define HWP_EPP_ENUM_ENABLE          (1 << HWP_EPP_SHIFT)
-#define LOCK_MISC_PWR_MGMT_MSR_SHIFT 13
-#define LOCK_MISC_PWR_MGMT_MSR       (1 << LOCK_MISC_PWR_MGMT_MSR_SHIFT)
-#define LOCK_THERM_INT_SHIFT         22
-#define LOCK_THERM_INT               (1 << LOCK_THERM_INT_SHIFT)
-
-/* MSR_TURBO_RATIO_LIMIT bits */
-#define MSR_TURBO_RATIO_LIMIT        0x1ad
-
-/* MSR_TURBO_RATIO_LIMIT_CORES (0x1ae) */
-#define MSR_TURBO_RATIO_LIMIT_CORES  0x1ae
-
-/* MSR_VR_CURRENT_CONFIG bits */
-#define MSR_VR_CURRENT_CONFIG        0x601
-#define CURRENT_LIMIT_LOCK_SHIFT     31
-#define CURRENT_LIMIT_LOCK           (0x1 << CURRENT_LIMIT_LOCK_SHIFT)
-
-/* MSR_TURBO_ACTIVATION_RATIO bits */
-#define MSR_TURBO_ACTIVATION_RATIO   0x64c
-#define MAX_NON_TURBO_RATIO_SHIFT    0
-#define MAX_NON_TURBO_RATIO          (0xff << MAX_NON_TURBO_RATIO_SHIFT)
-
-/* MSR_ENERGY_PERF_BIAS_CONFIG bits */
-#define MSR_ENERGY_PERF_BIAS_CONFIG  0xa01
-#define EPB_ENERGY_POLICY_SHIFT      3
-#define EPB_ENERGY_POLICY_MASK       (0xf << EPB_ENERGY_POLICY_SHIFT)
-
-#endif /* _SOC_MSR_H_ */
diff --git a/src/soc/intel/xeon_sp/include/soc/nvs.h b/src/soc/intel/xeon_sp/include/soc/nvs.h
deleted file mode 100644
index 613775c759..0000000000
--- a/src/soc/intel/xeon_sp/include/soc/nvs.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _SOC_NVS_H_
-#define _SOC_NVS_H_
-
-#include <stdint.h>
-
-/* TODO - this requires xeon sp, server board support */
-/* NOTE: We do not use intelblocks/nvs.h since it includes
-   mostly client specific attributes */
-typedef struct global_nvs_t {
-	uint8_t  pcnt;        /* 0x00 - Processor Count */
-	uint32_t cbmc;	      /* 0x01 - coreboot memconsole */
-	uint8_t rsvd3[251];
-} __packed global_nvs_t;
-
-#endif /* _SOC_NVS_H_ */
diff --git a/src/soc/intel/xeon_sp/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/include/soc/pci_devs.h
deleted file mode 100644
index fae7ca0279..0000000000
--- a/src/soc/intel/xeon_sp/include/soc/pci_devs.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_PCI_DEVS_H_
-#define _SOC_PCI_DEVS_H_
-
-#include <device/pci_def.h>
-#include <hob_iiouds.h>
-
-#define dump_csr(fmt, dev, reg) \
-	printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x\n", \
-		fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \
-		((uint32_t)dev >> 12) & 0x07, \
-		#reg, reg, pci_mmio_read_config32(dev, reg))
-
-#define dump_csr64(fmt, dev, reg) \
-	printk(BIOS_SPEW, "%s%x:%x:%x reg: %s (0x%x), data: 0x%x%x\n", \
-		fmt, ((uint32_t)dev >> 20) & 0xfff, ((uint32_t)dev >> 15) & 0x1f, \
-		((uint32_t)dev >> 12) & 0x07, #reg, reg, \
-		pci_mmio_read_config32(dev, reg+4), pci_mmio_read_config32(dev, reg))
-
-#define _SA_DEVFN(slot)         PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
-#define _PCH_DEVFN(slot, func)  PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
-
-#if !defined(__SIMPLE_DEVICE__)
-#include <device/device.h>
-#define _SA_DEV(slot)           pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__)
-#define _PCH_DEV(slot, func)    pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
-#else
-#include <arch/io.h>
-#define _SA_DEV(slot)           PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
-#define _PCH_DEV(slot, func)    PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
-#endif
-
-#define MMAP_VTD_CFG_REG_DEVID          0x2024
-#define VTD_DEV                         5
-#define VTD_FUNC                        0
-
-#define VTD_TOLM_CSR                    0xd0
-#define VTD_TSEG_BASE_CSR               0xa8
-#define VTD_TSEG_LIMIT_CSR              0xac
-#define VTD_EXT_CAP_LOW                 0x10
-#define VTD_MMCFG_BASE_CSR              0x90
-#define VTD_MMCFG_LIMIT_CSR             0x98
-#define VTD_TOHM_CSR                    0xd4
-#define VTD_MMIOL_CSR                   0xdc
-#define VTD_ME_BASE_CSR                 0xf0
-#define VTD_ME_LIMIT_CSR                0xf8
-#define VTD_VERSION                     0x00
-#define VTD_CAP                         0x08
-#define VTD_CAP_LOW                     0x08
-#define VTD_CAP_HIGH                    0x0C
-#define VTD_EXT_CAP_HIGH                0x14
-
-#define SAD_ALL_DEV                     29
-#define SAD_ALL_FUNC                    0
-#define SAD_ALL_PAM0123_CSR             0x40
-#define SAD_ALL_PAM456_CSR              0x44
-
-#define PCU_IIO_STACK                   1
-#define PCU_DEV                         30
-#define PCU_CR1_FUN                     1
-
-#define PCU_CR0_FUN                     0
-#define PCU_CR0_PLATFORM_INFO           0xa8
-#define PCU_CR0_P_STATE_LIMITS          0xd8
-#define P_STATE_LIMITS_LOCK_SHIFT       31
-#define P_STATE_LIMITS_LOCK             (1 << P_STATE_LIMITS_LOCK_SHIFT)
-#define PCU_CR0_TEMPERATURE_TARGET      0xe4
-#define PCU_CR0_PACKAGE_RAPL_LIMIT      0xe8
-#define PCU_CR0_CURRENT_CONFIG          0xf8
-#define MAX_NON_TURBO_LIM_RATIO_SHIFT   8 /* 8:15 */
-#define MAX_NON_TURBO_LIM_RATIO_MASK    (0xff << MAX_NON_TURBO_LIM_RATIO_SHIFT)
-
-#define PCU_CR1_BIOS_RESET_CPL_REG                         0x94
-#define   RST_CPL1_MASK                                    ((uint32_t)1 << 1)
-#define   RST_CPL2_MASK                                    ((uint32_t)1 << 2)
-#define   RST_CPL3_MASK                                    ((uint32_t)1 << 3)
-#define   RST_CPL4_MASK                                    ((uint32_t)1 << 4)
-#define   PCODE_INIT_DONE1_MASK                            ((uint32_t)1 << 9)
-#define   PCODE_INIT_DONE2_MASK                            ((uint32_t)1 << 10)
-#define   PCODE_INIT_DONE3_MASK                            ((uint32_t)1 << 11)
-#define   PCODE_INIT_DONE4_MASK                            ((uint32_t)1 << 12)
-
-#define PCU_CR1_BIOS_MB_DATA_REG                           0x8c
-
-#define PCU_CR1_BIOS_MB_INTERFACE_REG                      0x90
-#define   BIOS_MB_RUN_BUSY_MASK                            ((uint32_t)1 << 31)
-#define   BIOS_MB_CMD_MASK                                 ((uint32_t)0xff)
-#define   BIOS_CMD_READ_PCU_MISC_CFG                       0x5
-#define   BIOS_CMD_WRITE_PCU_MISC_CFG                      0x6
-#define   BIOS_ERR_INVALID_CMD                             0x01
-
-#define PCU_CR1_DESIRED_CORES_CFG2_REG                     0xa0
-#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK           ((uint32_t)1 << 31)
-
-#define PCU_CR1_C2C3TT_REG                                 0xdc
-#define PCU_CR1_PCIE_ILTR_OVRD                             0xfc
-#define PCU_CR1_SAPMCTL                                    0xb0
-#define SAPMCTL_LOCK_SHIFT                                 31
-#define SAPMCTL_LOCK_MASK                                  (1 << SAPMCTL_LOCK_SHIFT)
-#define PCU_CR1_MC_BIOS_REQ                                0x98
-
-#define PCU_CR2_FUN                                        2
-#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK                0x8c
-#define PCIE_IN_PKGCSTATE_L1_MASK                          0xFFFFFF /* 23:0 bits */
-#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2               0x90
-#define KTI_IN_PKGCSTATE_L1_MASK                           0x7 /* 2:0 bits */
-#define PCU_CR2_DYNAMIC_PERF_POWER_CTL                     0xdc
-#define UNCORE_PLIMIT_OVERRIDE_BIT                         20
-#define UNOCRE_PLIMIT_OVERRIDE_SHIFT                       (1 << UNCORE_PLIMIT_OVERRIDE_BIT)
-#define PCU_CR2_PROCHOT_RESPONSE_RATIO_REG                 0xb0
-#define PROCHOT_RATIO                                      0xa /* bits 0:7 */
-
-#define UBOX_DECS_BUS                                      0
-#define UBOX_DECS_DEV                                      8
-#define UBOX_DECS_FUNC                                     2
-#define UBOX_DECS_CPUBUSNO_CSR                             0xcc
-
-#define CHA_UTIL_ALL_DEV                                   29
-#define CHA_UTIL_ALL_FUNC                                  1
-#define CHA_UTIL_ALL_MMCFG_CSR                             0xc0
-
-#define CBDMA_DEV_NUM                                      0x04
-#define IIO_CBDMA_MMIO_SIZE                                0x10000 //64kB for one CBDMA function
-#define IIO_CBDMA_MMIO_ALIGNMENT                           14 //2^14 - 16kB
-
-#define VMD_DEV_NUM                                        5
-#define VMD_FUNC_NUM                                       5
-
-#define APIC_DEV_NUM                                       5
-#define APIC_FUNC_NUM                                      0
-
-#define PCH_IOAPIC_BUS_NUMBER                              0xF0
-#define PCH_IOAPIC_DEV_NUM                                 0x1F
-#define PCH_IOAPIC_FUNC_NUM                                0x00
-
-// ================================== IOAPIC Definitions for DMAR/ACPI ====================
-#define PCH_IOAPIC_ID                   0x08
-#define PC00_IOAPIC_ID                  0x09
-#define PC01_IOAPIC_ID                  0x0A
-#define PC02_IOAPIC_ID                  0x0B
-#define PC03_IOAPIC_ID                  0x0C
-#define PC04_IOAPIC_ID                  0x0D
-#define PC05_IOAPIC_ID                  0x0E
-#define PC06_IOAPIC_ID                  0x0F
-#define PC07_IOAPIC_ID                  0x10
-#define PC08_IOAPIC_ID                  0x11
-#define PC09_IOAPIC_ID                  0x12
-#define PC10_IOAPIC_ID                  0x13
-#define PC11_IOAPIC_ID                  0x14
-
-/* PCH Device info */
-
-#define  XHCI_BUS_NUMBER        0x0
-#define  PCH_DEV_SLOT_XHCI      0x14
-#define  XHCI_FUNC_NUM          0x0
-
-#define HPET_BUS_NUM            0x0
-#define HPET_DEV_NUM            PCH_DEV_SLOT_LPC
-#define HPET0_FUNC_NUM          0x00
-
-#define PCH_DEV_SLOT_LPC        0x1f
-#define  PCH_DEVFN_LPC          _PCH_DEVFN(LPC, 0)
-#define  PCH_DEVFN_P2SB         _PCH_DEVFN(LPC, 1)
-#define  PCH_DEVFN_PMC          _PCH_DEVFN(LPC, 2)
-#define  PCH_DEVFN_SPI          _PCH_DEVFN(LPC, 5)
-#define  PCH_DEV_LPC            _PCH_DEV(LPC, 0)
-#define  PCH_DEV_P2SB           _PCH_DEV(LPC, 1)
-#define  PCH_DEV_PMC            _PCH_DEV(LPC, 2)
-#define  PCH_DEV_SPI            _PCH_DEV(LPC, 5)
-
-#endif /* _SOC_PCI_DEVS_H_ */
diff --git a/src/soc/intel/xeon_sp/include/soc/ramstage.h b/src/soc/intel/xeon_sp/include/soc/ramstage.h
deleted file mode 100644
index cf615ff635..0000000000
--- a/src/soc/intel/xeon_sp/include/soc/ramstage.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_RAMSTAGE_H_
-#define _SOC_RAMSTAGE_H_
-
-#include <device/device.h>
-#include <fsp/api.h>
-#include <fsp/util.h>
-#include <memory_info.h>
-
-void xeon_sp_init_cpus(struct device *dev);
-void mainboard_silicon_init_params(FSPS_UPD *params);
-
-extern struct pci_operations soc_pci_ops;
-
-#endif
diff --git a/src/soc/intel/xeon_sp/include/soc/soc_util.h b/src/soc/intel/xeon_sp/include/soc/util.h
index 47e5be3172..6f907f6ff0 100644
--- a/src/soc/intel/xeon_sp/include/soc/soc_util.h
+++ b/src/soc/intel/xeon_sp/include/soc/util.h
@@ -13,13 +13,14 @@
  * GNU General Public License for more details.
  */
 
+#ifndef _XEON_SP_SOC_UTIL_H_
+#define _XEON_SP_SOC_UTIL_H_
 
-#ifndef _SOC_UTIL_H_
-#define _SOC_UTIL_H_
+#include <console/console.h>
 
-#include <hob_iiouds.h>
-#include <hob_memmap.h>
-#include <arch/acpi.h>
+void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3);
+void unlock_pam_regions(void);
+void get_stack_busnos(uint32_t *bus);
 
 #define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \
 	printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \
@@ -46,34 +47,4 @@
 #define FUNC_EXIT() \
 	printk(BIOS_SPEW, "%s:%s:%d: EXIT\n", __FILE__, __func__, __LINE__)
 
-struct iiostack_resource {
-	uint8_t     no_of_stacks;
-	STACK_RES   res[CONFIG_MAX_SOCKET * MAX_IIO_STACK];
-};
-
-uintptr_t get_tolm(uint32_t bus);
-void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit);
-uintptr_t get_cha_mmcfg_base(uint32_t bus);
-uint32_t top_of_32bit_ram(void); // Top of 32bit usable memory
-
-uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset);
-
-void get_stack_busnos(uint32_t *bus);
-void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3);
-uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack);
-void get_iiostack_info(struct iiostack_resource *info);
-
-int get_threads_per_package(void);
-int get_platform_thread_count(void);
-void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits);
-
-unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem);
-void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits,
-	uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread);
-
-void unlock_pam_regions(void);
-void xeonsp_init_cpu_config(void);
-void set_bios_init_completion(void);
-void config_reset_cpl3_csrs(void);
-
-#endif /* _SOC_UTIL_H_ */
+#endif