diff options
| author | Rocky Phagura <rphagura@fb.com> | 2020-10-08 13:32:41 -0700 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-24 12:44:28 +0000 |
| commit | 17a798b68cc6d475d5d0c14e1a4a39b14754203c (patch) | |
| tree | 756939e4342122d76eb74b71a552c7360b591fcd /src/soc/intel/xeon_sp/include | |
| parent | f4721246db125e08b5e60a8a38a08cb92c478bd3 (diff) | |
soc/intel/xeon_sp: Enable SMI handler
SMI handler was not installed for Xeon_sp platforms. This enables SMM
relocation and SMI handling.
TESTED:
- SMRR are correctly set
- The save state revision is correct (0x00030101)
- SMI's are properly generated and handled
- SMM MSR save state are not supported, so relocate SMM on all cores
in series
- Verified on OCP/Deltalake mainboard.
NOTE:
- Code for accessing a CPU save state is not working for SMMLOADERV2,
so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS
pointer are not supported.
- This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS
is broken and needs to be fixed separately. It is unknown if TCO is
supported. This might require a cleanup in the future.
Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46231
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/include')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/nvs.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/smmrelocate.h | 9 |
2 files changed, 13 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/nvs.h b/src/soc/intel/xeon_sp/include/soc/nvs.h index becdd76570..100a442178 100644 --- a/src/soc/intel/xeon_sp/include/soc/nvs.h +++ b/src/soc/intel/xeon_sp/include/soc/nvs.h @@ -8,10 +8,13 @@ /* TODO - this requires xeon sp, server board support */ /* NOTE: We do not use intelblocks/nvs.h since it includes mostly client specific attributes */ + +/* TODO: This is not aligned with the ACPI asl code */ struct __packed global_nvs { uint8_t pcnt; /* 0x00 - Processor Count */ uint32_t cbmc; /* 0x01 - coreboot memconsole */ - uint8_t rsvd3[251]; + uint8_t uior; + uint8_t rsvd3[250]; }; #endif /* _SOC_NVS_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/smmrelocate.h b/src/soc/intel/xeon_sp/include/soc/smmrelocate.h new file mode 100644 index 0000000000..314ebd49db --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/smmrelocate.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_SMMRELOCATE_H_ +#define _SOC_SMMRELOCATE_H_ + +void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, + size_t *smm_save_state_size); + +#endif |