soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration

Add PCIe enumeration and resource assignment/allocation.

Xeon-SP processor family has split IIO design, where PCIe domain 0 is
split into multiple stacks. Each stack has its own resource ranges (eg.
IO resource, mem32 resource, mem64 resource). The stack itself is not
PCIe device, it does not have config space to be probed/programmed.

The stack is programmed by FSP. coreboot needs to take into account of
stack when doing PCIe enumeration and resource allocation.

Current coreboot PCIe resource allocator does not support the concept of
split IIO stack, thus entire support is done locally in this patch.

In near future, improvements will be done, first generalize for xeon-sp,
then generalize for coreboot PCIe device code.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: If461b1dc1f313d98b676dc9e91d08a1dbb9cb388
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

1 files changed, 32 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c
new file mode 100644
index 0000000000..8548615239
--- /dev/null
+++ b/src/soc/intel/xeon_sp/cpx/soc_util.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <soc/soc_util.h>
+#include <stdlib.h>
+#include <string.h>
+
+uint8_t get_iiostack_info(struct iiostack_resource *info)
+{
+	size_t hob_size;
+	const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
+	const IIO_UDS *hob;
+
+	hob = fsp_find_extension_hob_by_guid(
+		fsp_hob_iio_universal_data_guid, &hob_size);
+	assert(hob != NULL && hob_size != 0);
+
+	// copy IIO Stack info from FSP HOB
+	info->no_of_stacks = 0;
+	for (int s = 0; s < hob->PlatformData.numofIIO; ++s) {
+		for (int x = 0; x < MAX_IIO_STACK; ++x) {
+			const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x];
+			// TODO: do we have situation with only bux 0 and one stack?
+			if (ri->BusBase >= ri->BusLimit)
+				continue;
+			assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK));
+			memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES));
+		}
+	}
+
+	return hob->PlatformData.Pci64BitResourceAllocation;
+}