diff options
author | Andrey Petrov <anpetrov@fb.com> | 2020-04-20 18:07:08 -0700 |
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committer | Andrey Petrov <andrey.petrov@gmail.com> | 2020-04-24 19:44:00 +0000 |
commit | dddb9a85bd1e9810410f14010f20c9ce2dabfee5 (patch) | |
tree | edc0f2328984b41c2a0f15a414158850b10ebc41 /src/soc/intel/xeon_sp/cpx/romstage.c | |
parent | 2f96970e1f4e586a4c5928fefab1bc0f98bc1351 (diff) |
soc/intel/xeon_sp/cpx: Work around FSP-M issues
Currently FSP-M does not implement the spec completely, e.g it is unable
to use user-provided heap location in CAR. While this is being resolved,
this workaround is a stop-gap solution that allows multi-socket usage.
TEST=tested on OCP Sonora Pass EVT and Intel Cedar Island CRB
Change-Id: Ia2529526a8724cf54377b0bd2339b04fa900815a
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40555
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/romstage.c')
-rw-r--r-- | src/soc/intel/xeon_sp/cpx/romstage.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index e909b87ca8..355554a782 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -9,8 +9,19 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; (void)m_cfg; + /* + * Currently FSP for CPX does not implement user-provided StackBase/Size + * properly. When KTI link needs to be trained, inter-socket communication + * library needs quite a bit of memory for its heap usage. However, location + * is hardcoded so this workaround is needed. + */ + if (CONFIG_MAX_SOCKET > 1) { + arch_upd->StackBase = (void *) 0xfe930000; + arch_upd->StackSize = 0x70000; + } mainboard_memory_init_params(mupd); } |