diff options
| author | Jingle Hsu <jingle_hsu@wiwynn.com> | 2020-08-11 20:48:45 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-18 08:48:04 +0000 |
| commit | a41b12cd7b8ffa1af1d7b0bc5eae799acd4f86da (patch) | |
| tree | 1429aceda89aff71f93458240d9b7dae0dce1fa8 /src/soc/intel/xeon_sp/cpx/include | |
| parent | 7749c34a11029c3cba6dbd280cd19852c57a304f (diff) | |
xeon_sp/cpx: Enable ACPI P-state support
Implement ACPI P-state support to enable driver acpi_cpufreq.
This patch leverages code from the Skylake project.
Tested=On OCP Delta Lake
cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
1501000 1500000 1400000 1300000 1200000 1100000 1000000 900000 800000
Change-Id: I3bf3ad7f82fbf196a2134a8138b10176fc8be2cc
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/include')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/include/soc/acpi.h | 6 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/include/soc/cpu.h | 3 |
2 files changed, 6 insertions, 3 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h b/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h index 2f923d47a1..6a76ef222b 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h @@ -11,6 +11,12 @@ typedef struct { uint8_t buf[32]; } MEM_BLK; +/* P-state configuration */ +#define PSS_MAX_ENTRIES 16 +#define PSS_RATIO_STEP 1 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index 3e740645ba..19f6e4c5d5 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -9,9 +9,6 @@ #define CPUID_COOPERLAKE_SP_A0 0x05065a #define CPUID_COOPERLAKE_SP_A1 0x05065b -/* CPU bus clock is fixed at 100MHz */ -#define CPU_BCLK 100 - void cpx_init_cpus(struct device *dev); msr_t read_msr_ppin(void); |