soc/intel/xeon_sp: Add basic Cooperlake-SP support

This adds barebones support.

What works:
* Linux kernel boots fine
* SIRQ and PCH interupts work fine (only in IOAPIC mode)
* PCH devices are usable

What doesn't:
* MP init is not there yet, only 1 CPU is up
* SMM is not supported
* GPIO is not available
* All IIO and extended bus numbers enumeration is not yet available
* Warm reset flow is untested
* MRC cache save/load

TEST=boots into Linux

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I7c987badc3c53f16ad178369c7e0906d6596e465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39713
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

6 files changed, 108 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h
new file mode 100644
index 0000000000..f33df89a60
--- /dev/null
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+/* nothing here yet */
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/gpio.h b/src/soc/intel/xeon_sp/cpx/include/soc/gpio.h
new file mode 100644
index 0000000000..36e1a703f5
--- /dev/null
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/gpio.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+/* not implemented, adding defaults just to make common code happy */
+
+#ifndef _SOC_GPIO_H_
+#define _SOC_GPIO_H
+
+#define GPIO_NUM_PAD_CFG_REGS		0
+#define NUM_GPI_STATUS_REGS		0
+
+#endif
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/irq.h b/src/soc/intel/xeon_sp/cpx/include/soc/irq.h
new file mode 100644
index 0000000000..14dd852b78
--- /dev/null
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/irq.h
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+/* nothing here, please come back later */
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h b/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h
new file mode 100644
index 0000000000..352bc27dad
--- /dev/null
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#ifndef _SOC_NVS_H_
+#define _SOC_NVS_H_
+
+#include <stdint.h>
+
+/* TODO - this requires xeon sp, server board support */
+/* NOTE: We do not use intelblocks/nvs.h since it includes
+   mostly client specific attributes */
+typedef struct global_nvs_t {
+	uint8_t  pcnt;        /* 0x00 - Processor Count */
+	uint32_t cbmc;	      /* 0x01 - coreboot memconsole */
+	uint8_t rsvd3[251];
+} __packed global_nvs_t;
+
+#endif /* _SOC_NVS_H_ */
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
new file mode 100644
index 0000000000..1154527e4c
--- /dev/null
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#ifndef _SOC_PCI_DEVS_H_
+#define _SOC_PCI_DEVS_H_
+
+#include <device/pci_def.h>
+
+#define _SA_DEVFN(slot)         PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
+#define _PCH_DEVFN(slot, func)  PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
+
+#if !defined(__SIMPLE_DEVICE__)
+#include <device/device.h>
+#define _SA_DEV(slot)           pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__)
+#define _PCH_DEV(slot, func)    pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__)
+#else
+#include <arch/io.h>
+#define _SA_DEV(slot)           PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
+#define _PCH_DEV(slot, func)    PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
+#endif
+
+#define SAD_ALL_DEV			29
+#define SAD_ALL_FUNC			0
+#define SAD_ALL_PAM0123_CSR		0x40
+#define SAD_ALL_PAM456_CSR		0x44
+
+#define UBOX_DECS_BUS			0
+#define UBOX_DECS_DEV			8
+#define UBOX_DECS_FUNC			2
+#define UBOX_DECS_CPUBUSNO_CSR		0xcc
+
+#define VTD_TOLM_CSR			0xd0
+#define VTD_TSEG_BASE_CSR		0xa8
+#define VTD_TSEG_LIMIT_CSR		0xac
+#define VTD_EXT_CAP_LOW			0x10
+#define VTD_MMCFG_BASE_CSR		0x90
+#define VTD_MMCFG_LIMIT_CSR		0x98
+#define VTD_TOHM_CSR			0xd4
+#define VTD_MMIOL_CSR			0xdc
+#define VTD_ME_BASE_CSR			0xf0
+#define VTD_ME_LIMIT_CSR		0xf8
+#define VTD_VERSION			0x00
+#define VTD_CAP				0x08
+#define VTD_CAP_LOW			0x08
+#define VTD_CAP_HIGH			0x0C
+#define VTD_EXT_CAP_HIGH		0x14
+
+#define MMAP_VTD_CFG_REG_DEVID		0x2024
+#define VTD_DEV				5
+#define VTD_FUNC			0
+
+
+
+#define PCH_DEV_SLOT_LPC        0x1f
+#define  PCH_DEVFN_LPC          _PCH_DEVFN(LPC, 0)
+#define  PCH_DEVFN_P2SB         _PCH_DEVFN(LPC, 1)
+#define  PCH_DEVFN_PMC          _PCH_DEVFN(LPC, 2)
+#define  PCH_DEVFN_SPI          _PCH_DEVFN(LPC, 5)
+#define  PCH_DEV_LPC            _PCH_DEV(LPC, 0)
+#define  PCH_DEV_P2SB           _PCH_DEV(LPC, 1)
+#define  PCH_DEV_PMC            _PCH_DEV(LPC, 2)
+#define  PCH_DEV_SPI            _PCH_DEV(LPC, 5)
+
+#endif /* _SOC_PCI_DEVS_H_ */
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h b/src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h
new file mode 100644
index 0000000000..28e8d1a1dc
--- /dev/null
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/ramstage.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <device/device.h>
+
+extern struct pci_operations soc_pci_ops;