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authorRocky Phagura <rphagura@fb.com>2020-10-08 13:32:41 -0700
committerArthur Heymans <arthur@aheymans.xyz>2020-11-24 12:44:28 +0000
commit17a798b68cc6d475d5d0c14e1a4a39b14754203c (patch)
tree756939e4342122d76eb74b71a552c7360b591fcd /src/soc/intel/xeon_sp/cpx/cpu.c
parentf4721246db125e08b5e60a8a38a08cb92c478bd3 (diff)
soc/intel/xeon_sp: Enable SMI handler
SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - SMI's are properly generated and handled - SMM MSR save state are not supported, so relocate SMM on all cores in series - Verified on OCP/Deltalake mainboard. NOTE: - Code for accessing a CPU save state is not working for SMMLOADERV2, so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS pointer are not supported. - This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS is broken and needs to be fixed separately. It is unknown if TCO is supported. This might require a cleanup in the future. Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura <rphagura@fb.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46231 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/cpu.c')
-rw-r--r--src/soc/intel/xeon_sp/cpx/cpu.c13
1 files changed, 8 insertions, 5 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index d1bcbd7977..2f4ab0663e 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -7,7 +7,9 @@
#include <console/debug.h>
#include <cpu/cpu.h>
#include <cpu/intel/common/common.h>
+#include <cpu/intel/em64t101_save_state.h>
#include <cpu/intel/microcode.h>
+#include <cpu/intel/smm_reloc.h>
#include <cpu/intel/turbo.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/mp.h>
@@ -17,6 +19,7 @@
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/soc_util.h>
+#include <soc/smmrelocate.h>
#include <soc/util.h>
#include "chip.h"
@@ -172,16 +175,16 @@ static void post_mp_init(void)
/* Set Max Ratio */
set_max_turbo_freq();
- /*
- * TODO: Now that all APs have been relocated as well as the BSP let SMIs
- * start flowing.
- */
- if (0) global_smi_enable();
+ if (CONFIG(HAVE_SMI_HANDLER))
+ global_smi_enable();
}
static const struct mp_ops mp_ops = {
.pre_mp_init = pre_mp_init,
.get_cpu_count = get_thread_count,
+ .get_smm_info = get_smm_info,
+ .pre_mp_smm_init = smm_initialize,
+ .relocation_handler = smm_relocation_handler,
.get_microcode_info = get_microcode_info,
.post_mp_init = post_mp_init,
};