diff options
| author | Andrey Petrov <anpetrov@fb.com> | 2020-03-30 12:25:06 -0700 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@gmail.com> | 2020-04-04 04:27:45 +0000 |
| commit | 8670e829a8f2f6e56c2405333a171c2bc7cd017b (patch) | |
| tree | 11bde530ae6212446d31aad71ad7d79eeac5fa5e /src/soc/intel/xeon_sp/cpx/Makefile.inc | |
| parent | ebda03ea5637cb2dd0b7426cbac72a4738ef7233 (diff) | |
soc/intel/xeon_sp/cpx: Add multi-core init
Add minimal MP init. No SMM, no turbo, not c/p states.
TEST=boot linux kernel, observe CPUs are online, schedule tasks
and perform useful work. Tested on Cedar Island CRB with only 1
socket populated
Change-Id: I0af374ab3956009e9208917d911d29eb21db6069
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/Makefile.inc')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/Makefile.inc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index b909a454bd..e00ae40637 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -8,9 +8,10 @@ ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y) subdirs-y += ../../../../cpu/x86/lapic subdirs-y += ../../../../cpu/x86/mtrr subdirs-y += ../../../../cpu/x86/tsc +subdirs-y += ../../../../cpu/intel/microcode romstage-y += romstage.c -ramstage-y += chip.c acpi.c +ramstage-y += chip.c acpi.c cpu.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx |