diff options
author | Rocky Phagura <rphagura@fb.com> | 2020-10-08 13:32:41 -0700 |
---|---|---|
committer | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-24 12:44:28 +0000 |
commit | 17a798b68cc6d475d5d0c14e1a4a39b14754203c (patch) | |
tree | 756939e4342122d76eb74b71a552c7360b591fcd /src/soc/intel/xeon_sp/cpx/Makefile.inc | |
parent | f4721246db125e08b5e60a8a38a08cb92c478bd3 (diff) |
soc/intel/xeon_sp: Enable SMI handler
SMI handler was not installed for Xeon_sp platforms. This enables SMM
relocation and SMI handling.
TESTED:
- SMRR are correctly set
- The save state revision is correct (0x00030101)
- SMI's are properly generated and handled
- SMM MSR save state are not supported, so relocate SMM on all cores
in series
- Verified on OCP/Deltalake mainboard.
NOTE:
- Code for accessing a CPU save state is not working for SMMLOADERV2,
so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS
pointer are not supported.
- This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS
is broken and needs to be fixed separately. It is unknown if TCO is
supported. This might require a cleanup in the future.
Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46231
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/Makefile.inc')
-rw-r--r-- | src/soc/intel/xeon_sp/cpx/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index b2e653e50e..a5c6848852 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -5,6 +5,7 @@ ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y) subdirs-y += ../../../../cpu/intel/turbo subdirs-y += ../../../../cpu/x86/lapic subdirs-y += ../../../../cpu/x86/mtrr +subdirs-y += ../../../../cpu/x86/smm subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/intel/microcode |