diff options
author | Johnny Lin <johnny_lin@wiwynn.com> | 2020-02-19 15:52:45 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-25 10:42:14 +0000 |
commit | ebb7f54b1a107816e4f83bc31f1631acb85700d1 (patch) | |
tree | 3568e691490943cc111b5ad590e0b74194a86a51 /src/soc/intel/xeon_sp/bootblock/bootblock.c | |
parent | 3180af7fd6a86d202c241b02afa9cc4c0b9d9262 (diff) |
soc/intel/xeon_sp: Enable LPC generic IO decode range
To use Intel common block LPC function that enables the IO ranges
defined in devicetree.cb.
Tested on OCP Tioga Pass with BMC LPC working.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I675489d3c66dad259e4101a17300176f6c0e8bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38994
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/bootblock/bootblock.c')
-rw-r--r-- | src/soc/intel/xeon_sp/bootblock/bootblock.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/bootblock/bootblock.c b/src/soc/intel/xeon_sp/bootblock/bootblock.c index dc88adc308..453c383897 100644 --- a/src/soc/intel/xeon_sp/bootblock/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock/bootblock.c @@ -20,6 +20,7 @@ #include <soc/iomap.h> #include <console/console.h> #include <cpu/x86/mtrr.h> +#include <intelblocks/lpc_lib.h> const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -52,6 +53,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) void bootblock_soc_early_init(void) { fast_spi_early_init(SPI_BASE_ADDRESS); + pch_enable_lpc(); } void bootblock_soc_init(void) |