soc/intel/xeon_sp: Use common ASL code for xeon_sp

Move and use the common xeon_sp/cpx/acpi asl for skx/.
There were only minor whitespace differences between the directories.

Update the mainboards to build the moved files.

TiogaPass coreboot.rom checked with BUILD_TIMELESS.

Change-Id: I5058a3fe8d96075a266fb92f10707bb94308c85b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45217
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 32 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/acpi/uncore.asl b/src/soc/intel/xeon_sp/acpi/uncore.asl
new file mode 100644
index 0000000000..b1b5f6c624
--- /dev/null
+++ b/src/soc/intel/xeon_sp/acpi/uncore.asl
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/itss.h>
+#include <intelblocks/pcr.h>
+#include <soc/iomap.h>
+#include <soc/irq.h>
+#include <soc/pcr_ids.h>
+
+Scope(\)
+{
+	// Private Chipset Register(PCR). Memory Mapped through ILB
+	OperationRegion(PCRR, SystemMemory, P2SB_BAR, 0x01000000)
+	Field(PCRR, DWordAcc, Lock, Preserve)
+	{
+		Offset (0xD03100),  // Interrupt Routing Registers
+		PRTA, 8,
+		PRTB, 8,
+		PRTC, 8,
+		PRTD, 8,
+		PRTE, 8,
+		PRTF, 8,
+		PRTG, 8,
+		PRTH, 8,
+	}
+}
+
+Scope (\_SB)
+{
+	#include "pci_irq.asl"
+	#include "uncore_irq.asl"
+	#include "iiostack.asl"
+}