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authorAndrey Petrov <anpetrov@fb.com>2020-03-16 22:46:57 -0700
committerAndrey Petrov <andrey.petrov@gmail.com>2020-03-26 02:06:45 +0000
commit662da6cf7b181ea2787ba001d9cbb6d41916abec (patch)
tree63a95b276913110c423c566db78b856650582ad3 /src/soc/intel/xeon_sp/acpi/uncore.asl
parenta1b15172d7f0303e8a1fe147a778d73d4dc26b1a (diff)
soc/intel/xeon_sp: Refactor code to allow for additional CPUs types
Refactor the code and split it into Xeon common and CPU-specific code. Move most Skylake-SP code into skx/ and keep common code in the current folder. This is a preparation for future work that will enable next generation server CPU. TEST=Tested on OCP Tioga Pass. There does not seem to be degradation of stability as far as I could tell. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/acpi/uncore.asl')
-rw-r--r--src/soc/intel/xeon_sp/acpi/uncore.asl46
1 files changed, 0 insertions, 46 deletions
diff --git a/src/soc/intel/xeon_sp/acpi/uncore.asl b/src/soc/intel/xeon_sp/acpi/uncore.asl
deleted file mode 100644
index ced1c4fd2b..0000000000
--- a/src/soc/intel/xeon_sp/acpi/uncore.asl
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#include <intelblocks/itss.h>
-#include <intelblocks/pcr.h>
-#include <soc/iomap.h>
-#include <soc/irq.h>
-#include <soc/pcr_ids.h>
-
-Scope(\)
-{
- // Private Chipset Register(PCR). Memory Mapped through ILB
- OperationRegion(PCRR, SystemMemory, P2SB_BAR, 0x01000000)
- Field(PCRR, DWordAcc, Lock, Preserve)
- {
- Offset (0xD03100), // Interrupt Routing Registers
- PRTA, 8,
- PRTB, 8,
- PRTC, 8,
- PRTD, 8,
- PRTE, 8,
- PRTF, 8,
- PRTG, 8,
- PRTH, 8,
- }
-}
-
-Scope (_SB)
-{
- #include "pci_irq.asl"
- #include "uncore_irq.asl"
- #include "iiostack.asl"
-}